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PK ѹ�ZBGǝ� � Kconfignu �[��� # SPDX-License-Identifier: GPL-2.0-only config VIDEO_DAVINCI_VPIF_DISPLAY tristate "TI DaVinci VPIF V4L2-Display driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF2_DMA_CONTIG select VIDEO_ADV7343 if MEDIA_SUBDRV_AUTOSELECT select VIDEO_THS7303 if MEDIA_SUBDRV_AUTOSELECT help Enables Davinci VPIF module used for display devices. This module is used for display on TI DM6467/DA850/OMAPL138 SoCs. To compile this driver as a module, choose M here. There will be two modules called vpif.ko and vpif_display.ko config VIDEO_DAVINCI_VPIF_CAPTURE tristate "TI DaVinci VPIF video capture driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF2_DMA_CONTIG select V4L2_FWNODE help Enables Davinci VPIF module used for capture devices. This module is used for capture on TI DM6467/DA850/OMAPL138 SoCs. To compile this driver as a module, choose M here. There will be two modules called vpif.ko and vpif_capture.ko config VIDEO_DM6446_CCDC tristate "TI DM6446 CCDC video capture driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF_DMA_CONTIG help Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces with decoder modules such as TVP5146 over BT656 or sensor module such as MT9T001 over a raw interface. This module configures the interface and CCDC/ISIF to do video frame capture from slave decoders. To compile this driver as a module, choose M here. There will be three modules called vpfe_capture.ko, vpss.ko and dm644x_ccdc.ko config VIDEO_DM355_CCDC tristate "TI DM355 CCDC video capture driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF_DMA_CONTIG help Enables DM355 CCD hw module. DM355 CCDC hw interfaces with decoder modules such as TVP5146 over BT656 or sensor module such as MT9T001 over a raw interface. This module configures the interface and CCDC/ISIF to do video frame capture from a slave decoders To compile this driver as a module, choose M here. There will be three modules called vpfe_capture.ko, vpss.ko and dm355_ccdc.ko config VIDEO_DM365_ISIF tristate "TI DM365 ISIF video capture driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF_DMA_CONTIG help Enables ISIF hw module. This is the hardware module for configuring ISIF in VPFE to capture Raw Bayer RGB data from a image sensor or YUV data from a YUV source. To compile this driver as a module, choose M here. There will be three modules called vpfe_capture.ko, vpss.ko and isif.ko config VIDEO_DAVINCI_VPBE_DISPLAY tristate "TI DaVinci VPBE V4L2-Display driver" depends on VIDEO_V4L2 depends on ARCH_DAVINCI || COMPILE_TEST depends on I2C select VIDEOBUF2_DMA_CONTIG help Enables Davinci VPBE module used for display devices. This module is used for display on TI DM644x/DM365/DM355 based display devices. To compile this driver as a module, choose M here. There will be five modules created called vpss.ko, vpbe.ko, vpbe_osd.ko, vpbe_venc.ko and vpbe_display.ko PK ѹ�Z(]��� � Makefilenu �[��� # SPDX-License-Identifier: GPL-2.0 ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o obj-y += pll.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o obj-y += psc.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o obj-$(CONFIG_ARCH_DAVINCI_DM644x) += psc-dm644x.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += psc-dm646x.o endif PK DJ�ZwqBb� � vpbe_venc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2010 Texas Instruments Inc */ #ifndef _VPBE_VENC_H #define _VPBE_VENC_H #include <media/v4l2-subdev.h> #include <media/davinci/vpbe_types.h> #define DM644X_VPBE_VENC_SUBDEV_NAME "dm644x,vpbe-venc" #define DM365_VPBE_VENC_SUBDEV_NAME "dm365,vpbe-venc" #define DM355_VPBE_VENC_SUBDEV_NAME "dm355,vpbe-venc" /* venc events */ #define VENC_END_OF_FRAME BIT(0) #define VENC_FIRST_FIELD BIT(1) #define VENC_SECOND_FIELD BIT(2) struct venc_platform_data { int (*setup_pinmux)(u32 if_type, int field); int (*setup_clock)(enum vpbe_enc_timings_type type, unsigned int pixclock); int (*setup_if_config)(u32 pixcode); /* Number of LCD outputs supported */ int num_lcd_outputs; struct vpbe_if_params *lcd_if_params; }; enum venc_ioctls { VENC_GET_FLD = 1, }; /* exported functions */ struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev, const char *venc_name); #endif PK DJ�Z���| | ccdc_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2008-2009 Texas Instruments Inc * **************************************************************************/ #ifndef _CCDC_TYPES_H #define _CCDC_TYPES_H enum ccdc_pixfmt { CCDC_PIXFMT_RAW, CCDC_PIXFMT_YCBCR_16BIT, CCDC_PIXFMT_YCBCR_8BIT }; enum ccdc_frmfmt { CCDC_FRMFMT_PROGRESSIVE, CCDC_FRMFMT_INTERLACED }; /* PIXEL ORDER IN MEMORY from LSB to MSB */ /* only applicable for 8-bit input mode */ enum ccdc_pixorder { CCDC_PIXORDER_YCBYCR, CCDC_PIXORDER_CBYCRY, }; enum ccdc_buftype { CCDC_BUFTYPE_FLD_INTERLEAVED, CCDC_BUFTYPE_FLD_SEPARATED }; #endif PK DJ�Z����� � vpbe_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2010 Texas Instruments Inc */ #ifndef _VPBE_TYPES_H #define _VPBE_TYPES_H enum vpbe_version { VPBE_VERSION_1 = 1, VPBE_VERSION_2, VPBE_VERSION_3, }; /* vpbe_timing_type - Timing types used in vpbe device */ enum vpbe_enc_timings_type { VPBE_ENC_STD = 0x1, VPBE_ENC_DV_TIMINGS = 0x4, /* Used when set timings through FB device interface */ VPBE_ENC_TIMINGS_INVALID = 0x8, }; /* * struct vpbe_enc_mode_info * @name: ptr to name string of the standard, "NTSC", "PAL" etc * @std: standard or non-standard mode. 1 - standard, 0 - nonstandard * @interlaced: 1 - interlaced, 0 - non interlaced/progressive * @xres: x or horizontal resolution of the display * @yres: y or vertical resolution of the display * @fps: frame per second * @left_margin: left margin of the display * @right_margin: right margin of the display * @upper_margin: upper margin of the display * @lower_margin: lower margin of the display * @hsync_len: h-sync length * @vsync_len: v-sync length * @flags: bit field: bit usage is documented below * * Description: * Structure holding timing and resolution information of a standard. * Used by vpbe_device to set required non-standard timing in the * venc when lcd controller output is connected to a external encoder. * A table of timings is maintained in vpbe device to set this in * venc when external encoder is connected to lcd controller output. * Encoder may provide a g_dv_timings() API to override these values * as needed. * * Notes * ------ * if_type should be used only by encoder manager and encoder. * flags usage * b0 (LSB) - hsync polarity, 0 - negative, 1 - positive * b1 - vsync polarity, 0 - negative, 1 - positive * b2 - field id polarity, 0 - negative, 1 - positive */ struct vpbe_enc_mode_info { unsigned char *name; enum vpbe_enc_timings_type timings_type; v4l2_std_id std_id; struct v4l2_dv_timings dv_timings; unsigned int interlaced; unsigned int xres; unsigned int yres; struct v4l2_fract aspect; struct v4l2_fract fps; unsigned int left_margin; unsigned int right_margin; unsigned int upper_margin; unsigned int lower_margin; unsigned int hsync_len; unsigned int vsync_len; unsigned int flags; }; #endif PK DJ�Z�c&a a vpfe_capture.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2008-2009 Texas Instruments Inc */ #ifndef _VPFE_CAPTURE_H #define _VPFE_CAPTURE_H #ifdef __KERNEL__ /* Header files */ #include <media/v4l2-dev.h> #include <linux/videodev2.h> #include <linux/clk.h> #include <linux/i2c.h> #include <media/v4l2-fh.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-device.h> #include <media/videobuf-dma-contig.h> #include <media/davinci/vpfe_types.h> #define VPFE_CAPTURE_NUM_DECODERS 5 /* Macros */ #define VPFE_MAJOR_RELEASE 0 #define VPFE_MINOR_RELEASE 0 #define VPFE_BUILD 1 #define VPFE_CAPTURE_VERSION_CODE ((VPFE_MAJOR_RELEASE << 16) | \ (VPFE_MINOR_RELEASE << 8) | \ VPFE_BUILD) #define CAPTURE_DRV_NAME "vpfe-capture" struct vpfe_pixel_format { u32 pixelformat; /* bytes per pixel */ int bpp; }; struct vpfe_std_info { int active_pixels; int active_lines; /* current frame format */ int frame_format; }; struct vpfe_route { u32 input; u32 output; }; struct vpfe_subdev_info { /* Sub device name */ char name[32]; /* Sub device group id */ int grp_id; /* Number of inputs supported */ int num_inputs; /* inputs available at the sub device */ struct v4l2_input *inputs; /* Sub dev routing information for each input */ struct vpfe_route *routes; /* check if sub dev supports routing */ int can_route; /* ccdc bus/interface configuration */ struct vpfe_hw_if_param ccdc_if_params; /* i2c subdevice board info */ struct i2c_board_info board_info; }; struct vpfe_config { /* Number of sub devices connected to vpfe */ int num_subdevs; /* i2c bus adapter no */ int i2c_adapter_id; /* information about each subdev */ struct vpfe_subdev_info *sub_devs; /* evm card info */ char *card_name; /* ccdc name */ char *ccdc; /* vpfe clock */ struct clk *vpssclk; struct clk *slaveclk; /* Function for Clearing the interrupt */ void (*clr_intr)(int vdint); }; struct vpfe_device { /* V4l2 specific parameters */ /* Identifies video device for this channel */ struct video_device video_dev; /* sub devices */ struct v4l2_subdev **sd; /* vpfe cfg */ struct vpfe_config *cfg; /* V4l2 device */ struct v4l2_device v4l2_dev; /* parent device */ struct device *pdev; /* number of open instances of the channel */ u32 usrs; /* Indicates id of the field which is being displayed */ u32 field_id; /* flag to indicate whether decoder is initialized */ u8 initialized; /* current interface type */ struct vpfe_hw_if_param vpfe_if_params; /* ptr to currently selected sub device */ struct vpfe_subdev_info *current_subdev; /* current input at the sub device */ int current_input; /* Keeps track of the information about the standard */ struct vpfe_std_info std_info; /* std index into std table */ int std_index; /* CCDC IRQs used when CCDC/ISIF output to SDRAM */ unsigned int ccdc_irq0; unsigned int ccdc_irq1; /* number of buffers in fbuffers */ u32 numbuffers; /* List of buffer pointers for storing frames */ u8 *fbuffers[VIDEO_MAX_FRAME]; /* Pointer pointing to current v4l2_buffer */ struct videobuf_buffer *cur_frm; /* Pointer pointing to next v4l2_buffer */ struct videobuf_buffer *next_frm; /* * This field keeps track of type of buffer exchange mechanism * user has selected */ enum v4l2_memory memory; /* Used to store pixel format */ struct v4l2_format fmt; /* * used when IMP is chained to store the crop window which * is different from the image window */ struct v4l2_rect crop; /* Buffer queue used in video-buf */ struct videobuf_queue buffer_queue; /* Queue of filled frames */ struct list_head dma_queue; /* Used in video-buf */ spinlock_t irqlock; /* IRQ lock for DMA queue */ spinlock_t dma_queue_lock; /* lock used to access this structure */ struct mutex lock; /* number of users performing IO */ u32 io_usrs; /* Indicates whether streaming started */ u8 started; /* * offset where second field starts from the starting of the * buffer for field separated YCbCr formats */ u32 field_off; }; /* File handle structure */ struct vpfe_fh { struct v4l2_fh fh; struct vpfe_device *vpfe_dev; /* Indicates whether this file handle is doing IO */ u8 io_allowed; }; struct vpfe_config_params { u8 min_numbuffers; u8 numbuffers; u32 min_bufsize; u32 device_bufsize; }; #endif /* End of __KERNEL__ */ #endif /* _DAVINCI_VPFE_H */ PK DJ�Z\O�\� � vpbe.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2010 Texas Instruments Inc */ #ifndef _VPBE_H #define _VPBE_H #include <linux/videodev2.h> #include <linux/i2c.h> #include <media/v4l2-dev.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-device.h> #include <media/davinci/vpbe_osd.h> #include <media/davinci/vpbe_venc.h> #include <media/davinci/vpbe_types.h> /* OSD configuration info */ struct osd_config_info { char module_name[32]; }; struct vpbe_output { struct v4l2_output output; /* * If output capabilities include dv_timings, list supported timings * below */ char *subdev_name; /* * defualt_mode identifies the default timings set at the venc or * external encoder. */ char *default_mode; /* * Fields below are used for supporting multiple modes. For example, * LCD panel might support different modes and they are listed here. * Similarly for supporting external encoders, lcd controller port * requires a set of non-standard timing values to be listed here for * each supported mode since venc is used in non-standard timing mode * for interfacing with external encoder similar to configuring lcd * panel timings */ unsigned int num_modes; struct vpbe_enc_mode_info *modes; /* * Bus configuration goes here for external encoders. Some encoders * may require multiple interface types for each of the output. For * example, SD modes would use YCC8 where as HD mode would use YCC16. * Not sure if this is needed on a per mode basis instead of per * output basis. If per mode is needed, we may have to move this to * mode_info structure */ u32 if_params; }; /* encoder configuration info */ struct encoder_config_info { char module_name[32]; /* Is this an i2c device ? */ unsigned int is_i2c:1; /* i2c subdevice board info */ struct i2c_board_info board_info; }; /*amplifier configuration info */ struct amp_config_info { char module_name[32]; /* Is this an i2c device ? */ unsigned int is_i2c:1; /* i2c subdevice board info */ struct i2c_board_info board_info; }; /* structure for defining vpbe display subsystem components */ struct vpbe_config { char module_name[32]; /* i2c bus adapter no */ int i2c_adapter_id; struct osd_config_info osd; struct encoder_config_info venc; /* external encoder information goes here */ int num_ext_encoders; struct encoder_config_info *ext_encoders; /* amplifier information goes here */ struct amp_config_info *amp; unsigned int num_outputs; /* Order is venc outputs followed by LCD and then external encoders */ struct vpbe_output *outputs; }; struct vpbe_device; struct vpbe_device_ops { /* Enumerate the outputs */ int (*enum_outputs)(struct vpbe_device *vpbe_dev, struct v4l2_output *output); /* Set output to the given index */ int (*set_output)(struct vpbe_device *vpbe_dev, int index); /* Get current output */ unsigned int (*get_output)(struct vpbe_device *vpbe_dev); /* Set DV preset at current output */ int (*s_dv_timings)(struct vpbe_device *vpbe_dev, struct v4l2_dv_timings *dv_timings); /* Get DV presets supported at the output */ int (*g_dv_timings)(struct vpbe_device *vpbe_dev, struct v4l2_dv_timings *dv_timings); /* Enumerate the DV Presets supported at the output */ int (*enum_dv_timings)(struct vpbe_device *vpbe_dev, struct v4l2_enum_dv_timings *timings_info); /* Set std at the output */ int (*s_std)(struct vpbe_device *vpbe_dev, v4l2_std_id std_id); /* Get the current std at the output */ int (*g_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id); /* initialize the device */ int (*initialize)(struct device *dev, struct vpbe_device *vpbe_dev); /* De-initialize the device */ void (*deinitialize)(struct device *dev, struct vpbe_device *vpbe_dev); /* Get the current mode info */ int (*get_mode_info)(struct vpbe_device *vpbe_dev, struct vpbe_enc_mode_info*); /* * Set the current mode in the encoder. Alternate way of setting * standard or DV preset or custom timings in the encoder */ int (*set_mode)(struct vpbe_device *vpbe_dev, struct vpbe_enc_mode_info*); /* Power management operations */ int (*suspend)(struct vpbe_device *vpbe_dev); int (*resume)(struct vpbe_device *vpbe_dev); }; /* struct for vpbe device */ struct vpbe_device { /* V4l2 device */ struct v4l2_device v4l2_dev; /* vpbe dispay controller cfg */ struct vpbe_config *cfg; /* parent device */ struct device *pdev; /* external encoder v4l2 sub devices */ struct v4l2_subdev **encoders; /* current encoder index */ int current_sd_index; /* external amplifier v4l2 subdevice */ struct v4l2_subdev *amp; struct mutex lock; /* device initialized */ int initialized; /* vpbe dac clock */ struct clk *dac_clk; /* osd_device pointer */ struct osd_state *osd_device; /* venc device pointer */ struct venc_platform_data *venc_device; /* * fields below are accessed by users of vpbe_device. Not the * ones above */ /* current output */ int current_out_index; /* lock used by caller to do atomic operation on vpbe device */ /* current timings set in the controller */ struct vpbe_enc_mode_info current_timings; /* venc sub device */ struct v4l2_subdev *venc; /* device operations below */ struct vpbe_device_ops ops; }; #endif PK DJ�ZU��P� � vpfe_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2008-2009 Texas Instruments Inc */ #ifndef _VPFE_TYPES_H #define _VPFE_TYPES_H #ifdef __KERNEL__ enum vpfe_pin_pol { VPFE_PINPOL_POSITIVE, VPFE_PINPOL_NEGATIVE }; enum vpfe_hw_if_type { /* BT656 - 8 bit */ VPFE_BT656, /* BT1120 - 16 bit */ VPFE_BT1120, /* Raw Bayer */ VPFE_RAW_BAYER, /* YCbCr - 8 bit with external sync */ VPFE_YCBCR_SYNC_8, /* YCbCr - 16 bit with external sync */ VPFE_YCBCR_SYNC_16, /* BT656 - 10 bit */ VPFE_BT656_10BIT }; /* interface description */ struct vpfe_hw_if_param { enum vpfe_hw_if_type if_type; enum vpfe_pin_pol hdpol; enum vpfe_pin_pol vdpol; }; #endif #endif PK DJ�Z}�p� � vpbe_display.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef VPBE_DISPLAY_H #define VPBE_DISPLAY_H /* Header files */ #include <linux/videodev2.h> #include <media/v4l2-common.h> #include <media/v4l2-fh.h> #include <media/videobuf2-v4l2.h> #include <media/videobuf2-dma-contig.h> #include <media/davinci/vpbe_types.h> #include <media/davinci/vpbe_osd.h> #include <media/davinci/vpbe.h> #define VPBE_DISPLAY_MAX_DEVICES 2 enum vpbe_display_device_id { VPBE_DISPLAY_DEVICE_0, VPBE_DISPLAY_DEVICE_1 }; #define VPBE_DISPLAY_DRV_NAME "vpbe-display" #define VPBE_DISPLAY_MAJOR_RELEASE 1 #define VPBE_DISPLAY_MINOR_RELEASE 0 #define VPBE_DISPLAY_BUILD 1 #define VPBE_DISPLAY_VERSION_CODE ((VPBE_DISPLAY_MAJOR_RELEASE << 16) | \ (VPBE_DISPLAY_MINOR_RELEASE << 8) | \ VPBE_DISPLAY_BUILD) #define VPBE_DISPLAY_VALID_FIELD(field) ((V4L2_FIELD_NONE == field) || \ (V4L2_FIELD_ANY == field) || (V4L2_FIELD_INTERLACED == field)) /* Exp ratio numerator and denominator constants */ #define VPBE_DISPLAY_H_EXP_RATIO_N 9 #define VPBE_DISPLAY_H_EXP_RATIO_D 8 #define VPBE_DISPLAY_V_EXP_RATIO_N 6 #define VPBE_DISPLAY_V_EXP_RATIO_D 5 /* Zoom multiplication factor */ #define VPBE_DISPLAY_ZOOM_4X 4 #define VPBE_DISPLAY_ZOOM_2X 2 /* Structures */ struct display_layer_info { int enable; /* Layer ID used by Display Manager */ enum osd_layer id; struct osd_layer_config config; enum osd_zoom_factor h_zoom; enum osd_zoom_factor v_zoom; enum osd_h_exp_ratio h_exp; enum osd_v_exp_ratio v_exp; }; struct vpbe_disp_buffer { struct vb2_v4l2_buffer vb; struct list_head list; }; /* vpbe display object structure */ struct vpbe_layer { /* Pointer to the vpbe_display */ struct vpbe_display *disp_dev; /* Pointer pointing to current v4l2_buffer */ struct vpbe_disp_buffer *cur_frm; /* Pointer pointing to next v4l2_buffer */ struct vpbe_disp_buffer *next_frm; /* videobuf specific parameters * Buffer queue used in video-buf */ struct vb2_queue buffer_queue; /* Queue of filled frames */ struct list_head dma_queue; /* Used in video-buf */ spinlock_t irqlock; /* V4l2 specific parameters */ /* Identifies video device for this layer */ struct video_device video_dev; /* Used to store pixel format */ struct v4l2_pix_format pix_fmt; enum v4l2_field buf_field; /* Video layer configuration params */ struct display_layer_info layer_info; /* vpbe specific parameters * enable window for display */ unsigned char window_enable; /* number of open instances of the layer */ unsigned int usrs; /* Indicates id of the field which is being displayed */ unsigned int field_id; /* Identifies device object */ enum vpbe_display_device_id device_id; /* facilitation of ioctl ops lock by v4l2*/ struct mutex opslock; u8 layer_first_int; }; /* vpbe device structure */ struct vpbe_display { /* layer specific parameters */ /* lock for isr updates to buf layers*/ spinlock_t dma_queue_lock; /* C-Plane offset from start of y-plane */ unsigned int cbcr_ofst; struct vpbe_layer *dev[VPBE_DISPLAY_MAX_DEVICES]; struct vpbe_device *vpbe_dev; struct osd_state *osd_device; }; struct buf_config_params { unsigned char min_numbuffers; unsigned char numbuffers[VPBE_DISPLAY_MAX_DEVICES]; unsigned int min_bufsize[VPBE_DISPLAY_MAX_DEVICES]; unsigned int layer_bufsize[VPBE_DISPLAY_MAX_DEVICES]; }; #endif /* VPBE_DISPLAY_H */ PK DJ�Z57f{ { dm355_ccdc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2005-2009 Texas Instruments Inc */ #ifndef _DM355_CCDC_H #define _DM355_CCDC_H #include <media/davinci/ccdc_types.h> #include <media/davinci/vpfe_types.h> /* enum for No of pixel per line to be avg. in Black Clamping */ enum ccdc_sample_length { CCDC_SAMPLE_1PIXELS, CCDC_SAMPLE_2PIXELS, CCDC_SAMPLE_4PIXELS, CCDC_SAMPLE_8PIXELS, CCDC_SAMPLE_16PIXELS }; /* enum for No of lines in Black Clamping */ enum ccdc_sample_line { CCDC_SAMPLE_1LINES, CCDC_SAMPLE_2LINES, CCDC_SAMPLE_4LINES, CCDC_SAMPLE_8LINES, CCDC_SAMPLE_16LINES }; /* enum for Alaw gamma width */ enum ccdc_gamma_width { CCDC_GAMMA_BITS_13_4, CCDC_GAMMA_BITS_12_3, CCDC_GAMMA_BITS_11_2, CCDC_GAMMA_BITS_10_1, CCDC_GAMMA_BITS_09_0 }; enum ccdc_colpats { CCDC_RED, CCDC_GREEN_RED, CCDC_GREEN_BLUE, CCDC_BLUE }; struct ccdc_col_pat { enum ccdc_colpats olop; enum ccdc_colpats olep; enum ccdc_colpats elop; enum ccdc_colpats elep; }; enum ccdc_datasft { CCDC_DATA_NO_SHIFT, CCDC_DATA_SHIFT_1BIT, CCDC_DATA_SHIFT_2BIT, CCDC_DATA_SHIFT_3BIT, CCDC_DATA_SHIFT_4BIT, CCDC_DATA_SHIFT_5BIT, CCDC_DATA_SHIFT_6BIT }; enum ccdc_data_size { CCDC_DATA_16BITS, CCDC_DATA_15BITS, CCDC_DATA_14BITS, CCDC_DATA_13BITS, CCDC_DATA_12BITS, CCDC_DATA_11BITS, CCDC_DATA_10BITS, CCDC_DATA_8BITS }; enum ccdc_mfilt1 { CCDC_NO_MEDIAN_FILTER1, CCDC_AVERAGE_FILTER1, CCDC_MEDIAN_FILTER1 }; enum ccdc_mfilt2 { CCDC_NO_MEDIAN_FILTER2, CCDC_AVERAGE_FILTER2, CCDC_MEDIAN_FILTER2 }; /* structure for ALaw */ struct ccdc_a_law { /* Enable/disable A-Law */ unsigned char enable; /* Gamma Width Input */ enum ccdc_gamma_width gamma_wd; }; /* structure for Black Clamping */ struct ccdc_black_clamp { /* only if bClampEnable is TRUE */ unsigned char b_clamp_enable; /* only if bClampEnable is TRUE */ enum ccdc_sample_length sample_pixel; /* only if bClampEnable is TRUE */ enum ccdc_sample_line sample_ln; /* only if bClampEnable is TRUE */ unsigned short start_pixel; /* only if bClampEnable is FALSE */ unsigned short sgain; unsigned short dc_sub; }; /* structure for Black Level Compensation */ struct ccdc_black_compensation { /* Constant value to subtract from Red component */ unsigned char r; /* Constant value to subtract from Gr component */ unsigned char gr; /* Constant value to subtract from Blue component */ unsigned char b; /* Constant value to subtract from Gb component */ unsigned char gb; }; struct ccdc_float { int integer; unsigned int decimal; }; #define CCDC_CSC_COEFF_TABLE_SIZE 16 /* structure for color space converter */ struct ccdc_csc { unsigned char enable; /* * S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99. * example - to use 1.03, set integer part as 1, and decimal part as 3 * to use -1.03, set integer part as -1 and decimal part as 3 */ struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE]; }; /* Structures for Vertical Defect Correction*/ enum ccdc_vdf_csl { CCDC_VDF_NORMAL, CCDC_VDF_HORZ_INTERPOL_SAT, CCDC_VDF_HORZ_INTERPOL }; enum ccdc_vdf_cuda { CCDC_VDF_WHOLE_LINE_CORRECT, CCDC_VDF_UPPER_DISABLE }; enum ccdc_dfc_mwr { CCDC_DFC_MWR_WRITE_COMPLETE, CCDC_DFC_WRITE_REG }; enum ccdc_dfc_mrd { CCDC_DFC_READ_COMPLETE, CCDC_DFC_READ_REG }; enum ccdc_dfc_ma_rst { CCDC_DFC_INCR_ADDR, CCDC_DFC_CLR_ADDR }; enum ccdc_dfc_mclr { CCDC_DFC_CLEAR_COMPLETE, CCDC_DFC_CLEAR }; struct ccdc_dft_corr_ctl { enum ccdc_vdf_csl vdfcsl; enum ccdc_vdf_cuda vdfcuda; unsigned int vdflsft; }; struct ccdc_dft_corr_mem_ctl { enum ccdc_dfc_mwr dfcmwr; enum ccdc_dfc_mrd dfcmrd; enum ccdc_dfc_ma_rst dfcmarst; enum ccdc_dfc_mclr dfcmclr; }; #define CCDC_DFT_TABLE_SIZE 16 /* * Main Structure for vertical defect correction. Vertical defect * correction can correct up to 16 defects if defects less than 16 * then pad the rest with 0 */ struct ccdc_vertical_dft { unsigned char ver_dft_en; unsigned char gen_dft_en; unsigned int saturation_ctl; struct ccdc_dft_corr_ctl dft_corr_ctl; struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl; int table_size; unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE]; unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE]; unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE]; unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE]; unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE]; }; struct ccdc_data_offset { unsigned char horz_offset; unsigned char vert_offset; }; /* * Structure for CCDC configuration parameters for raw capture mode passed * by application */ struct ccdc_config_params_raw { /* data shift to be applied before storing */ enum ccdc_datasft datasft; /* data size value from 8 to 16 bits */ enum ccdc_data_size data_sz; /* median filter for sdram */ enum ccdc_mfilt1 mfilt1; enum ccdc_mfilt2 mfilt2; /* low pass filter enable/disable */ unsigned char lpf_enable; /* Threshold of median filter */ int med_filt_thres; /* * horz and vertical data offset. Applicable for defect correction * and lsc */ struct ccdc_data_offset data_offset; /* Structure for Optional A-Law */ struct ccdc_a_law alaw; /* Structure for Optical Black Clamp */ struct ccdc_black_clamp blk_clamp; /* Structure for Black Compensation */ struct ccdc_black_compensation blk_comp; /* structure for vertical Defect Correction Module Configuration */ struct ccdc_vertical_dft vertical_dft; /* structure for color space converter Module Configuration */ struct ccdc_csc csc; /* color patters for bayer capture */ struct ccdc_col_pat col_pat_field0; struct ccdc_col_pat col_pat_field1; }; #ifdef __KERNEL__ #include <linux/io.h> #define CCDC_WIN_PAL {0, 0, 720, 576} #define CCDC_WIN_VGA {0, 0, 640, 480} struct ccdc_params_ycbcr { /* pixel format */ enum ccdc_pixfmt pix_fmt; /* progressive or interlaced frame */ enum ccdc_frmfmt frm_fmt; /* video window */ struct v4l2_rect win; /* field id polarity */ enum vpfe_pin_pol fid_pol; /* vertical sync polarity */ enum vpfe_pin_pol vd_pol; /* horizontal sync polarity */ enum vpfe_pin_pol hd_pol; /* enable BT.656 embedded sync mode */ int bt656_enable; /* cb:y:cr:y or y:cb:y:cr in memory */ enum ccdc_pixorder pix_order; /* interleaved or separated fields */ enum ccdc_buftype buf_type; }; /* Gain applied to Raw Bayer data */ struct ccdc_gain { unsigned short r_ye; unsigned short gr_cy; unsigned short gb_g; unsigned short b_mg; }; /* Structure for CCDC configuration parameters for raw capture mode */ struct ccdc_params_raw { /* pixel format */ enum ccdc_pixfmt pix_fmt; /* progressive or interlaced frame */ enum ccdc_frmfmt frm_fmt; /* video window */ struct v4l2_rect win; /* field id polarity */ enum vpfe_pin_pol fid_pol; /* vertical sync polarity */ enum vpfe_pin_pol vd_pol; /* horizontal sync polarity */ enum vpfe_pin_pol hd_pol; /* interleaved or separated fields */ enum ccdc_buftype buf_type; /* Gain values */ struct ccdc_gain gain; /* offset */ unsigned int ccdc_offset; /* horizontal flip enable */ unsigned char horz_flip_enable; /* * enable to store the image in inverse order in memory * (bottom to top) */ unsigned char image_invert_enable; /* Configurable part of raw data */ struct ccdc_config_params_raw config_params; }; #endif #endif /* DM355_CCDC_H */ PK DJ�Z� I�T T vpif_types.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2011 Texas Instruments Inc */ #ifndef _VPIF_TYPES_H #define _VPIF_TYPES_H #include <linux/i2c.h> #define VPIF_CAPTURE_MAX_CHANNELS 2 #define VPIF_DISPLAY_MAX_CHANNELS 2 enum vpif_if_type { VPIF_IF_BT656, VPIF_IF_BT1120, VPIF_IF_RAW_BAYER }; struct vpif_interface { enum vpif_if_type if_type; unsigned hd_pol:1; unsigned vd_pol:1; unsigned fid_pol:1; }; struct vpif_subdev_info { const char *name; struct i2c_board_info board_info; }; struct vpif_output { struct v4l2_output output; const char *subdev_name; u32 input_route; u32 output_route; }; struct vpif_display_chan_config { const struct vpif_output *outputs; int output_count; bool clip_en; }; struct vpif_display_config { int (*set_clock)(int, int); struct vpif_subdev_info *subdevinfo; int subdev_count; int i2c_adapter_id; struct vpif_display_chan_config chan_config[VPIF_DISPLAY_MAX_CHANNELS]; const char *card_name; }; struct vpif_input { struct v4l2_input input; char *subdev_name; u32 input_route; u32 output_route; }; struct vpif_capture_chan_config { struct vpif_interface vpif_if; struct vpif_input *inputs; int input_count; }; struct vpif_capture_config { int (*setup_input_channel_mode)(int); int (*setup_input_path)(int, const char *); struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; struct vpif_subdev_info *subdev_info; int subdev_count; int i2c_adapter_id; const char *card_name; struct v4l2_async_subdev *asd[VPIF_CAPTURE_MAX_CHANNELS]; int asd_sizes[VPIF_CAPTURE_MAX_CHANNELS]; }; #endif /* _VPIF_TYPES_H */ PK DJ�Z, D��7 �7 isif.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2008-2009 Texas Instruments Inc * * isif header file */ #ifndef _ISIF_H #define _ISIF_H #include <media/davinci/ccdc_types.h> #include <media/davinci/vpfe_types.h> /* isif float type S8Q8/U8Q8 */ struct isif_float_8 { /* 8 bit integer part */ __u8 integer; /* 8 bit decimal part */ __u8 decimal; }; /* isif float type U16Q16/S16Q16 */ struct isif_float_16 { /* 16 bit integer part */ __u16 integer; /* 16 bit decimal part */ __u16 decimal; }; /************************************************************************ * Vertical Defect Correction parameters ***********************************************************************/ /* Defect Correction (DFC) table entry */ struct isif_vdfc_entry { /* vertical position of defect */ __u16 pos_vert; /* horizontal position of defect */ __u16 pos_horz; /* * Defect level of Vertical line defect position. This is subtracted * from the data at the defect position */ __u8 level_at_pos; /* * Defect level of the pixels upper than the vertical line defect. * This is subtracted from the data */ __u8 level_up_pixels; /* * Defect level of the pixels lower than the vertical line defect. * This is subtracted from the data */ __u8 level_low_pixels; }; #define ISIF_VDFC_TABLE_SIZE 8 struct isif_dfc { /* enable vertical defect correction */ __u8 en; /* Defect level subtraction. Just fed through if saturating */ #define ISIF_VDFC_NORMAL 0 /* * Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2 * if data saturating */ #define ISIF_VDFC_HORZ_INTERPOL_IF_SAT 1 /* Horizontal interpolation (((i-2)+(i+2))/2) */ #define ISIF_VDFC_HORZ_INTERPOL 2 /* one of the vertical defect correction modes above */ __u8 corr_mode; /* 0 - whole line corrected, 1 - not pixels upper than the defect */ __u8 corr_whole_line; #define ISIF_VDFC_NO_SHIFT 0 #define ISIF_VDFC_SHIFT_1 1 #define ISIF_VDFC_SHIFT_2 2 #define ISIF_VDFC_SHIFT_3 3 #define ISIF_VDFC_SHIFT_4 4 /* * defect level shift value. level_at_pos, level_upper_pos, * and level_lower_pos can be shifted up by this value. Choose * one of the values above */ __u8 def_level_shift; /* defect saturation level */ __u16 def_sat_level; /* number of vertical defects. Max is ISIF_VDFC_TABLE_SIZE */ __u16 num_vdefects; /* VDFC table ptr */ struct isif_vdfc_entry table[ISIF_VDFC_TABLE_SIZE]; }; struct isif_horz_bclamp { /* Horizontal clamp disabled. Only vertical clamp value is subtracted */ #define ISIF_HORZ_BC_DISABLE 0 /* * Horizontal clamp value is calculated and subtracted from image data * along with vertical clamp value */ #define ISIF_HORZ_BC_CLAMP_CALC_ENABLED 1 /* * Horizontal clamp value calculated from previous image is subtracted * from image data along with vertical clamp value. */ #define ISIF_HORZ_BC_CLAMP_NOT_UPDATED 2 /* horizontal clamp mode. One of the values above */ __u8 mode; /* * pixel value limit enable. * 0 - limit disabled * 1 - pixel value limited to 1023 */ __u8 clamp_pix_limit; /* Select Most left window for bc calculation */ #define ISIF_SEL_MOST_LEFT_WIN 0 /* Select Most right window for bc calculation */ #define ISIF_SEL_MOST_RIGHT_WIN 1 /* Select most left or right window for clamp val calculation */ __u8 base_win_sel_calc; /* Window count per color for calculation. range 1-32 */ __u8 win_count_calc; /* Window start position - horizontal for calculation. 0 - 8191 */ __u16 win_start_h_calc; /* Window start position - vertical for calculation 0 - 8191 */ __u16 win_start_v_calc; #define ISIF_HORZ_BC_SZ_H_2PIXELS 0 #define ISIF_HORZ_BC_SZ_H_4PIXELS 1 #define ISIF_HORZ_BC_SZ_H_8PIXELS 2 #define ISIF_HORZ_BC_SZ_H_16PIXELS 3 /* Width of the sample window in pixels for calculation */ __u8 win_h_sz_calc; #define ISIF_HORZ_BC_SZ_V_32PIXELS 0 #define ISIF_HORZ_BC_SZ_V_64PIXELS 1 #define ISIF_HORZ_BC_SZ_V_128PIXELS 2 #define ISIF_HORZ_BC_SZ_V_256PIXELS 3 /* Height of the sample window in pixels for calculation */ __u8 win_v_sz_calc; }; /************************************************************************ * Black Clamp parameters ***********************************************************************/ struct isif_vert_bclamp { /* Reset value used is the clamp value calculated */ #define ISIF_VERT_BC_USE_HORZ_CLAMP_VAL 0 /* Reset value used is reset_clamp_val configured */ #define ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL 1 /* No update, previous image value is used */ #define ISIF_VERT_BC_NO_UPDATE 2 /* * Reset value selector for vertical clamp calculation. Use one of * the above values */ __u8 reset_val_sel; /* U8Q8. Line average coefficient used in vertical clamp calculation */ __u8 line_ave_coef; /* Height of the optical black region for calculation */ __u16 ob_v_sz_calc; /* Optical black region start position - horizontal. 0 - 8191 */ __u16 ob_start_h; /* Optical black region start position - vertical 0 - 8191 */ __u16 ob_start_v; }; struct isif_black_clamp { /* * This offset value is added irrespective of the clamp enable status. * S13 */ __u16 dc_offset; /* * Enable black/digital clamp value to be subtracted from the image data */ __u8 en; /* * black clamp mode. same/separate clamp for 4 colors * 0 - disable - same clamp value for all colors * 1 - clamp value calculated separately for all colors */ __u8 bc_mode_color; /* Vertical start position for bc subtraction */ __u16 vert_start_sub; /* Black clamp for horizontal direction */ struct isif_horz_bclamp horz; /* Black clamp for vertical direction */ struct isif_vert_bclamp vert; }; /************************************************************************* ** Color Space Conversion (CSC) *************************************************************************/ #define ISIF_CSC_NUM_COEFF 16 struct isif_color_space_conv { /* Enable color space conversion */ __u8 en; /* * csc coefficient table. S8Q5, M00 at index 0, M01 at index 1, and * so forth */ struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF]; }; /************************************************************************* ** Black Compensation parameters *************************************************************************/ struct isif_black_comp { /* Comp for Red */ __s8 r_comp; /* Comp for Gr */ __s8 gr_comp; /* Comp for Blue */ __s8 b_comp; /* Comp for Gb */ __s8 gb_comp; }; /************************************************************************* ** Gain parameters *************************************************************************/ struct isif_gain { /* Gain for Red or ye */ struct isif_float_16 r_ye; /* Gain for Gr or cy */ struct isif_float_16 gr_cy; /* Gain for Gb or g */ struct isif_float_16 gb_g; /* Gain for Blue or mg */ struct isif_float_16 b_mg; }; #define ISIF_LINEAR_TAB_SIZE 192 /************************************************************************* ** Linearization parameters *************************************************************************/ struct isif_linearize { /* Enable or Disable linearization of data */ __u8 en; /* Shift value applied */ __u8 corr_shft; /* scale factor applied U11Q10 */ struct isif_float_16 scale_fact; /* Size of the linear table */ __u16 table[ISIF_LINEAR_TAB_SIZE]; }; /* Color patterns */ #define ISIF_RED 0 #define ISIF_GREEN_RED 1 #define ISIF_GREEN_BLUE 2 #define ISIF_BLUE 3 struct isif_col_pat { __u8 olop; __u8 olep; __u8 elop; __u8 elep; }; /************************************************************************* ** Data formatter parameters *************************************************************************/ struct isif_fmtplen { /* * number of program entries for SET0, range 1 - 16 * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is * ISIF_COMBINE */ __u16 plen0; /* * number of program entries for SET1, range 1 - 16 * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is * ISIF_COMBINE */ __u16 plen1; /** * number of program entries for SET2, range 1 - 16 * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is * ISIF_COMBINE */ __u16 plen2; /** * number of program entries for SET3, range 1 - 16 * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is * ISIF_COMBINE */ __u16 plen3; }; struct isif_fmt_cfg { #define ISIF_SPLIT 0 #define ISIF_COMBINE 1 /* Split or combine or line alternate */ __u8 fmtmode; /* enable or disable line alternating mode */ __u8 ln_alter_en; #define ISIF_1LINE 0 #define ISIF_2LINES 1 #define ISIF_3LINES 2 #define ISIF_4LINES 3 /* Split/combine line number */ __u8 lnum; /* Address increment Range 1 - 16 */ __u8 addrinc; }; struct isif_fmt_addr_ptr { /* Initial address */ __u32 init_addr; /* output line number */ #define ISIF_1STLINE 0 #define ISIF_2NDLINE 1 #define ISIF_3RDLINE 2 #define ISIF_4THLINE 3 __u8 out_line; }; struct isif_fmtpgm_ap { /* program address pointer */ __u8 pgm_aptr; /* program address increment or decrement */ __u8 pgmupdt; }; struct isif_data_formatter { /* Enable/Disable data formatter */ __u8 en; /* data formatter configuration */ struct isif_fmt_cfg cfg; /* Formatter program entries length */ struct isif_fmtplen plen; /* first pixel in a line fed to formatter */ __u16 fmtrlen; /* HD interval for output line. Only valid when split line */ __u16 fmthcnt; /* formatter address pointers */ struct isif_fmt_addr_ptr fmtaddr_ptr[16]; /* program enable/disable */ __u8 pgm_en[32]; /* program address pointers */ struct isif_fmtpgm_ap fmtpgm_ap[32]; }; struct isif_df_csc { /* Color Space Conversion configuration, 0 - csc, 1 - df */ __u8 df_or_csc; /* csc configuration valid if df_or_csc is 0 */ struct isif_color_space_conv csc; /* data formatter configuration valid if df_or_csc is 1 */ struct isif_data_formatter df; /* start pixel in a line at the input */ __u32 start_pix; /* number of pixels in input line */ __u32 num_pixels; /* start line at the input */ __u32 start_line; /* number of lines at the input */ __u32 num_lines; }; struct isif_gain_offsets_adj { /* Gain adjustment per color */ struct isif_gain gain; /* Offset adjustment */ __u16 offset; /* Enable or Disable Gain adjustment for SDRAM data */ __u8 gain_sdram_en; /* Enable or Disable Gain adjustment for IPIPE data */ __u8 gain_ipipe_en; /* Enable or Disable Gain adjustment for H3A data */ __u8 gain_h3a_en; /* Enable or Disable Gain adjustment for SDRAM data */ __u8 offset_sdram_en; /* Enable or Disable Gain adjustment for IPIPE data */ __u8 offset_ipipe_en; /* Enable or Disable Gain adjustment for H3A data */ __u8 offset_h3a_en; }; struct isif_cul { /* Horizontal Cull pattern for odd lines */ __u8 hcpat_odd; /* Horizontal Cull pattern for even lines */ __u8 hcpat_even; /* Vertical Cull pattern */ __u8 vcpat; /* Enable or disable lpf. Apply when cull is enabled */ __u8 en_lpf; }; struct isif_compress { #define ISIF_ALAW 0 #define ISIF_DPCM 1 #define ISIF_NO_COMPRESSION 2 /* Compression Algorithm used */ __u8 alg; /* Choose Predictor1 for DPCM compression */ #define ISIF_DPCM_PRED1 0 /* Choose Predictor2 for DPCM compression */ #define ISIF_DPCM_PRED2 1 /* Predictor for DPCM compression */ __u8 pred; }; /* all the stuff in this struct will be provided by userland */ struct isif_config_params_raw { /* Linearization parameters for image sensor data input */ struct isif_linearize linearize; /* Data formatter or CSC */ struct isif_df_csc df_csc; /* Defect Pixel Correction (DFC) configuration */ struct isif_dfc dfc; /* Black/Digital Clamp configuration */ struct isif_black_clamp bclamp; /* Gain, offset adjustments */ struct isif_gain_offsets_adj gain_offset; /* Culling */ struct isif_cul culling; /* A-Law and DPCM compression options */ struct isif_compress compress; /* horizontal offset for Gain/LSC/DFC */ __u16 horz_offset; /* vertical offset for Gain/LSC/DFC */ __u16 vert_offset; /* color pattern for field 0 */ struct isif_col_pat col_pat_field0; /* color pattern for field 1 */ struct isif_col_pat col_pat_field1; #define ISIF_NO_SHIFT 0 #define ISIF_1BIT_SHIFT 1 #define ISIF_2BIT_SHIFT 2 #define ISIF_3BIT_SHIFT 3 #define ISIF_4BIT_SHIFT 4 #define ISIF_5BIT_SHIFT 5 #define ISIF_6BIT_SHIFT 6 /* Data shift applied before storing to SDRAM */ __u8 data_shift; /* enable input test pattern generation */ __u8 test_pat_gen; }; #ifdef __KERNEL__ struct isif_ycbcr_config { /* isif pixel format */ enum ccdc_pixfmt pix_fmt; /* isif frame format */ enum ccdc_frmfmt frm_fmt; /* ISIF crop window */ struct v4l2_rect win; /* field polarity */ enum vpfe_pin_pol fid_pol; /* interface VD polarity */ enum vpfe_pin_pol vd_pol; /* interface HD polarity */ enum vpfe_pin_pol hd_pol; /* isif pix order. Only used for ycbcr capture */ enum ccdc_pixorder pix_order; /* isif buffer type. Only used for ycbcr capture */ enum ccdc_buftype buf_type; }; /* MSB of image data connected to sensor port */ enum isif_data_msb { ISIF_BIT_MSB_15, ISIF_BIT_MSB_14, ISIF_BIT_MSB_13, ISIF_BIT_MSB_12, ISIF_BIT_MSB_11, ISIF_BIT_MSB_10, ISIF_BIT_MSB_9, ISIF_BIT_MSB_8, ISIF_BIT_MSB_7 }; enum isif_cfa_pattern { ISIF_CFA_PAT_MOSAIC, ISIF_CFA_PAT_STRIPE }; struct isif_params_raw { /* isif pixel format */ enum ccdc_pixfmt pix_fmt; /* isif frame format */ enum ccdc_frmfmt frm_fmt; /* video window */ struct v4l2_rect win; /* field polarity */ enum vpfe_pin_pol fid_pol; /* interface VD polarity */ enum vpfe_pin_pol vd_pol; /* interface HD polarity */ enum vpfe_pin_pol hd_pol; /* buffer type. Applicable for interlaced mode */ enum ccdc_buftype buf_type; /* Gain values */ struct isif_gain gain; /* cfa pattern */ enum isif_cfa_pattern cfa_pat; /* Data MSB position */ enum isif_data_msb data_msb; /* Enable horizontal flip */ unsigned char horz_flip_en; /* Enable image invert vertically */ unsigned char image_invert_en; /* all the userland defined stuff*/ struct isif_config_params_raw config_params; }; enum isif_data_pack { ISIF_PACK_16BIT, ISIF_PACK_12BIT, ISIF_PACK_8BIT }; #define ISIF_WIN_NTSC {0, 0, 720, 480} #define ISIF_WIN_VGA {0, 0, 640, 480} #endif #endif PK DJ�Zٙ{6�& �& vpbe_osd.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2007-2009 Texas Instruments Inc * Copyright (C) 2007 MontaVista Software, Inc. * * Andy Lowe (alowe@mvista.com), MontaVista Software * - Initial version * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd. * - ported to sub device interface */ #ifndef _OSD_H #define _OSD_H #include <media/davinci/vpbe_types.h> #define DM644X_VPBE_OSD_SUBDEV_NAME "dm644x,vpbe-osd" #define DM365_VPBE_OSD_SUBDEV_NAME "dm365,vpbe-osd" #define DM355_VPBE_OSD_SUBDEV_NAME "dm355,vpbe-osd" /** * enum osd_layer * @WIN_OSD0: On-Screen Display Window 0 * @WIN_VID0: Video Window 0 * @WIN_OSD1: On-Screen Display Window 1 * @WIN_VID1: Video Window 1 * * Description: * An enumeration of the osd display layers. */ enum osd_layer { WIN_OSD0, WIN_VID0, WIN_OSD1, WIN_VID1, }; /** * enum osd_win_layer * @OSDWIN_OSD0: On-Screen Display Window 0 * @OSDWIN_OSD1: On-Screen Display Window 1 * * Description: * An enumeration of the OSD Window layers. */ enum osd_win_layer { OSDWIN_OSD0, OSDWIN_OSD1, }; /** * enum osd_pix_format * @PIXFMT_1BPP: 1-bit-per-pixel bitmap * @PIXFMT_2BPP: 2-bits-per-pixel bitmap * @PIXFMT_4BPP: 4-bits-per-pixel bitmap * @PIXFMT_8BPP: 8-bits-per-pixel bitmap * @PIXFMT_RGB565: 16-bits-per-pixel RGB565 * @PIXFMT_YCBCRI: YUV 4:2:2 * @PIXFMT_RGB888: 24-bits-per-pixel RGB888 * @PIXFMT_YCRCBI: YUV 4:2:2 with chroma swap * @PIXFMT_NV12: YUV 4:2:0 planar * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp) * * Description: * An enumeration of the DaVinci pixel formats. */ enum osd_pix_format { PIXFMT_1BPP = 0, PIXFMT_2BPP, PIXFMT_4BPP, PIXFMT_8BPP, PIXFMT_RGB565, PIXFMT_YCBCRI, PIXFMT_RGB888, PIXFMT_YCRCBI, PIXFMT_NV12, PIXFMT_OSD_ATTR, }; /** * enum osd_h_exp_ratio * @H_EXP_OFF: no expansion (1/1) * @H_EXP_9_OVER_8: 9/8 expansion ratio * @H_EXP_3_OVER_2: 3/2 expansion ratio * * Description: * An enumeration of the available horizontal expansion ratios. */ enum osd_h_exp_ratio { H_EXP_OFF, H_EXP_9_OVER_8, H_EXP_3_OVER_2, }; /** * enum osd_v_exp_ratio * @V_EXP_OFF: no expansion (1/1) * @V_EXP_6_OVER_5: 6/5 expansion ratio * * Description: * An enumeration of the available vertical expansion ratios. */ enum osd_v_exp_ratio { V_EXP_OFF, V_EXP_6_OVER_5, }; /** * enum osd_zoom_factor * @ZOOM_X1: no zoom (x1) * @ZOOM_X2: x2 zoom * @ZOOM_X4: x4 zoom * * Description: * An enumeration of the available zoom factors. */ enum osd_zoom_factor { ZOOM_X1, ZOOM_X2, ZOOM_X4, }; /** * enum osd_clut * @ROM_CLUT: ROM CLUT * @RAM_CLUT: RAM CLUT * * Description: * An enumeration of the available Color Lookup Tables (CLUTs). */ enum osd_clut { ROM_CLUT, RAM_CLUT, }; /** * enum osd_rom_clut * @ROM_CLUT0: Macintosh CLUT * @ROM_CLUT1: CLUT from DM270 and prior devices * * Description: * An enumeration of the ROM Color Lookup Table (CLUT) options. */ enum osd_rom_clut { ROM_CLUT0, ROM_CLUT1, }; /** * enum osd_blending_factor * @OSD_0_VID_8: OSD pixels are fully transparent * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8 * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8 * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8 * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8 * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8 * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8 * @OSD_8_VID_0: OSD pixels are fully opaque * * Description: * An enumeration of the DaVinci pixel blending factor options. */ enum osd_blending_factor { OSD_0_VID_8, OSD_1_VID_7, OSD_2_VID_6, OSD_3_VID_5, OSD_4_VID_4, OSD_5_VID_3, OSD_6_VID_2, OSD_8_VID_0, }; /** * enum osd_blink_interval * @BLINK_X1: blink interval is 1 vertical refresh cycle * @BLINK_X2: blink interval is 2 vertical refresh cycles * @BLINK_X3: blink interval is 3 vertical refresh cycles * @BLINK_X4: blink interval is 4 vertical refresh cycles * * Description: * An enumeration of the DaVinci pixel blinking interval options. */ enum osd_blink_interval { BLINK_X1, BLINK_X2, BLINK_X3, BLINK_X4, }; /** * enum osd_cursor_h_width * @H_WIDTH_1: horizontal line width is 1 pixel * @H_WIDTH_4: horizontal line width is 4 pixels * @H_WIDTH_8: horizontal line width is 8 pixels * @H_WIDTH_12: horizontal line width is 12 pixels * @H_WIDTH_16: horizontal line width is 16 pixels * @H_WIDTH_20: horizontal line width is 20 pixels * @H_WIDTH_24: horizontal line width is 24 pixels * @H_WIDTH_28: horizontal line width is 28 pixels */ enum osd_cursor_h_width { H_WIDTH_1, H_WIDTH_4, H_WIDTH_8, H_WIDTH_12, H_WIDTH_16, H_WIDTH_20, H_WIDTH_24, H_WIDTH_28, }; /** * enum osd_cursor_v_width * @V_WIDTH_1: vertical line width is 1 line * @V_WIDTH_2: vertical line width is 2 lines * @V_WIDTH_4: vertical line width is 4 lines * @V_WIDTH_6: vertical line width is 6 lines * @V_WIDTH_8: vertical line width is 8 lines * @V_WIDTH_10: vertical line width is 10 lines * @V_WIDTH_12: vertical line width is 12 lines * @V_WIDTH_14: vertical line width is 14 lines */ enum osd_cursor_v_width { V_WIDTH_1, V_WIDTH_2, V_WIDTH_4, V_WIDTH_6, V_WIDTH_8, V_WIDTH_10, V_WIDTH_12, V_WIDTH_14, }; /** * struct osd_cursor_config * @xsize: horizontal size in pixels * @ysize: vertical size in lines * @xpos: horizontal offset in pixels from the left edge of the display * @ypos: vertical offset in lines from the top of the display * @interlaced: Non-zero if the display is interlaced, or zero otherwise * @h_width: horizontal line width * @v_width: vertical line width * @clut: the CLUT selector (ROM or RAM) for the cursor color * @clut_index: an index into the CLUT for the cursor color * * Description: * A structure describing the configuration parameters of the hardware * rectangular cursor. */ struct osd_cursor_config { unsigned xsize; unsigned ysize; unsigned xpos; unsigned ypos; int interlaced; enum osd_cursor_h_width h_width; enum osd_cursor_v_width v_width; enum osd_clut clut; unsigned char clut_index; }; /** * struct osd_layer_config * @pixfmt: pixel format * @line_length: offset in bytes between start of each line in memory * @xsize: number of horizontal pixels displayed per line * @ysize: number of lines displayed * @xpos: horizontal offset in pixels from the left edge of the display * @ypos: vertical offset in lines from the top of the display * @interlaced: Non-zero if the display is interlaced, or zero otherwise * * Description: * A structure describing the configuration parameters of an On-Screen Display * (OSD) or video layer related to how the image is stored in memory. * @line_length must be a multiple of the cache line size (32 bytes). */ struct osd_layer_config { enum osd_pix_format pixfmt; unsigned line_length; unsigned xsize; unsigned ysize; unsigned xpos; unsigned ypos; int interlaced; }; /* parameters that apply on a per-window (OSD or video) basis */ struct osd_window_state { int is_allocated; int is_enabled; unsigned long fb_base_phys; enum osd_zoom_factor h_zoom; enum osd_zoom_factor v_zoom; struct osd_layer_config lconfig; }; /* parameters that apply on a per-OSD-window basis */ struct osd_osdwin_state { enum osd_clut clut; enum osd_blending_factor blend; int colorkey_blending; unsigned colorkey; int rec601_attenuation; /* index is pixel value */ unsigned char palette_map[16]; }; /* hardware rectangular cursor parameters */ struct osd_cursor_state { int is_enabled; struct osd_cursor_config config; }; struct osd_state; struct vpbe_osd_ops { int (*initialize)(struct osd_state *sd); int (*request_layer)(struct osd_state *sd, enum osd_layer layer); void (*release_layer)(struct osd_state *sd, enum osd_layer layer); int (*enable_layer)(struct osd_state *sd, enum osd_layer layer, int otherwin); void (*disable_layer)(struct osd_state *sd, enum osd_layer layer); int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer, struct osd_layer_config *lconfig); void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer, struct osd_layer_config *lconfig); void (*start_layer)(struct osd_state *sd, enum osd_layer layer, unsigned long fb_base_phys, unsigned long cbcr_ofst); void (*set_left_margin)(struct osd_state *sd, u32 val); void (*set_top_margin)(struct osd_state *sd, u32 val); void (*set_interpolation_filter)(struct osd_state *sd, int filter); int (*set_vid_expansion)(struct osd_state *sd, enum osd_h_exp_ratio h_exp, enum osd_v_exp_ratio v_exp); void (*get_vid_expansion)(struct osd_state *sd, enum osd_h_exp_ratio *h_exp, enum osd_v_exp_ratio *v_exp); void (*set_zoom)(struct osd_state *sd, enum osd_layer layer, enum osd_zoom_factor h_zoom, enum osd_zoom_factor v_zoom); }; struct osd_state { enum vpbe_version vpbe_type; spinlock_t lock; struct device *dev; dma_addr_t osd_base_phys; void __iomem *osd_base; unsigned long osd_size; /* 1-->the isr will toggle the VID0 ping-pong buffer */ int pingpong; int interpolation_filter; int field_inversion; enum osd_h_exp_ratio osd_h_exp; enum osd_v_exp_ratio osd_v_exp; enum osd_h_exp_ratio vid_h_exp; enum osd_v_exp_ratio vid_v_exp; enum osd_clut backg_clut; unsigned backg_clut_index; enum osd_rom_clut rom_clut; int is_blinking; /* attribute window blinking enabled */ enum osd_blink_interval blink; /* YCbCrI or YCrCbI */ enum osd_pix_format yc_pixfmt; /* columns are Y, Cb, Cr */ unsigned char clut_ram[256][3]; struct osd_cursor_state cursor; /* OSD0, VID0, OSD1, VID1 */ struct osd_window_state win[4]; /* OSD0, OSD1 */ struct osd_osdwin_state osdwin[2]; /* OSD device Operations */ struct vpbe_osd_ops ops; }; struct osd_platform_data { int field_inv_wa_enable; }; #endif PK DJ�Z���/ / dm644x_ccdc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2006-2009 Texas Instruments Inc */ #ifndef _DM644X_CCDC_H #define _DM644X_CCDC_H #include <media/davinci/ccdc_types.h> #include <media/davinci/vpfe_types.h> /* enum for No of pixel per line to be avg. in Black Clamping*/ enum ccdc_sample_length { CCDC_SAMPLE_1PIXELS, CCDC_SAMPLE_2PIXELS, CCDC_SAMPLE_4PIXELS, CCDC_SAMPLE_8PIXELS, CCDC_SAMPLE_16PIXELS }; /* enum for No of lines in Black Clamping */ enum ccdc_sample_line { CCDC_SAMPLE_1LINES, CCDC_SAMPLE_2LINES, CCDC_SAMPLE_4LINES, CCDC_SAMPLE_8LINES, CCDC_SAMPLE_16LINES }; /* enum for Alaw gamma width */ enum ccdc_gamma_width { CCDC_GAMMA_BITS_15_6, /* use bits 15-6 for gamma */ CCDC_GAMMA_BITS_14_5, CCDC_GAMMA_BITS_13_4, CCDC_GAMMA_BITS_12_3, CCDC_GAMMA_BITS_11_2, CCDC_GAMMA_BITS_10_1, CCDC_GAMMA_BITS_09_0 /* use bits 9-0 for gamma */ }; /* returns the highest bit used for the gamma */ static inline u8 ccdc_gamma_width_max_bit(enum ccdc_gamma_width width) { return 15 - width; } enum ccdc_data_size { CCDC_DATA_16BITS, CCDC_DATA_15BITS, CCDC_DATA_14BITS, CCDC_DATA_13BITS, CCDC_DATA_12BITS, CCDC_DATA_11BITS, CCDC_DATA_10BITS, CCDC_DATA_8BITS }; /* returns the highest bit used for this data size */ static inline u8 ccdc_data_size_max_bit(enum ccdc_data_size sz) { return sz == CCDC_DATA_8BITS ? 7 : 15 - sz; } /* structure for ALaw */ struct ccdc_a_law { /* Enable/disable A-Law */ unsigned char enable; /* Gamma Width Input */ enum ccdc_gamma_width gamma_wd; }; /* structure for Black Clamping */ struct ccdc_black_clamp { unsigned char enable; /* only if bClampEnable is TRUE */ enum ccdc_sample_length sample_pixel; /* only if bClampEnable is TRUE */ enum ccdc_sample_line sample_ln; /* only if bClampEnable is TRUE */ unsigned short start_pixel; /* only if bClampEnable is TRUE */ unsigned short sgain; /* only if bClampEnable is FALSE */ unsigned short dc_sub; }; /* structure for Black Level Compensation */ struct ccdc_black_compensation { /* Constant value to subtract from Red component */ char r; /* Constant value to subtract from Gr component */ char gr; /* Constant value to subtract from Blue component */ char b; /* Constant value to subtract from Gb component */ char gb; }; /* Structure for CCDC configuration parameters for raw capture mode passed * by application */ struct ccdc_config_params_raw { /* data size value from 8 to 16 bits */ enum ccdc_data_size data_sz; /* Structure for Optional A-Law */ struct ccdc_a_law alaw; /* Structure for Optical Black Clamp */ struct ccdc_black_clamp blk_clamp; /* Structure for Black Compensation */ struct ccdc_black_compensation blk_comp; }; #ifdef __KERNEL__ #include <linux/io.h> /* Define to enable/disable video port */ #define FP_NUM_BYTES 4 /* Define for extra pixel/line and extra lines/frame */ #define NUM_EXTRAPIXELS 8 #define NUM_EXTRALINES 8 /* settings for commonly used video formats */ #define CCDC_WIN_PAL {0, 0, 720, 576} /* ntsc square pixel */ #define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)} /* Structure for CCDC configuration parameters for raw capture mode */ struct ccdc_params_raw { /* pixel format */ enum ccdc_pixfmt pix_fmt; /* progressive or interlaced frame */ enum ccdc_frmfmt frm_fmt; /* video window */ struct v4l2_rect win; /* field id polarity */ enum vpfe_pin_pol fid_pol; /* vertical sync polarity */ enum vpfe_pin_pol vd_pol; /* horizontal sync polarity */ enum vpfe_pin_pol hd_pol; /* interleaved or separated fields */ enum ccdc_buftype buf_type; /* * enable to store the image in inverse * order in memory(bottom to top) */ unsigned char image_invert_enable; /* configurable parameters */ struct ccdc_config_params_raw config_params; }; struct ccdc_params_ycbcr { /* pixel format */ enum ccdc_pixfmt pix_fmt; /* progressive or interlaced frame */ enum ccdc_frmfmt frm_fmt; /* video window */ struct v4l2_rect win; /* field id polarity */ enum vpfe_pin_pol fid_pol; /* vertical sync polarity */ enum vpfe_pin_pol vd_pol; /* horizontal sync polarity */ enum vpfe_pin_pol hd_pol; /* enable BT.656 embedded sync mode */ int bt656_enable; /* cb:y:cr:y or y:cb:y:cr in memory */ enum ccdc_pixorder pix_order; /* interleaved or separated fields */ enum ccdc_buftype buf_type; }; #endif #endif /* _DM644X_CCDC_H */ PK DJ�Z�'(�Y Y vpss.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2009 Texas Instruments Inc * * vpss - video processing subsystem module header file. * * Include this header file if a driver needs to configure vpss system * module. It exports a set of library functions for video drivers to * configure vpss system module functions such as clock enable/disable, * vpss interrupt mux to arm, and other common vpss system module * functions. */ #ifndef _VPSS_H #define _VPSS_H /* selector for ccdc input selection on DM355 */ enum vpss_ccdc_source_sel { VPSS_CCDCIN, VPSS_HSSIIN, VPSS_PGLPBK, /* for DM365 only */ VPSS_CCDCPG /* for DM365 only */ }; struct vpss_sync_pol { unsigned int ccdpg_hdpol:1; unsigned int ccdpg_vdpol:1; }; struct vpss_pg_frame_size { short hlpfr; short pplen; }; /* Used for enable/disable VPSS Clock */ enum vpss_clock_sel { /* DM355/DM365 */ VPSS_CCDC_CLOCK, VPSS_IPIPE_CLOCK, VPSS_H3A_CLOCK, VPSS_CFALD_CLOCK, /* * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api * following applies:- * en = 0 selects ENC_CLK * en = 1 selects ENC_CLK/2 */ VPSS_VENC_CLOCK_SEL, VPSS_VPBE_CLOCK, /* DM365 only clocks */ VPSS_IPIPEIF_CLOCK, VPSS_RSZ_CLOCK, VPSS_BL_CLOCK, /* * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api * following applies:- * en = 0 disable internal PCLK * en = 1 enables internal PCLK */ VPSS_PCLK_INTERNAL, /* * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api * following applies:- * en = 0 enables MMR clock * en = 1 enables VPSS clock */ VPSS_PSYNC_CLOCK_SEL, VPSS_LDC_CLOCK_SEL, VPSS_OSD_CLOCK_SEL, VPSS_FDIF_CLOCK, VPSS_LDC_CLOCK }; /* select input to ccdc on dm355 */ int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel); /* enable/disable a vpss clock, 0 - success, -1 - failure */ int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en); /* set sync polarity, only for DM365*/ void dm365_vpss_set_sync_pol(struct vpss_sync_pol); /* set the PG_FRAME_SIZE register, only for DM365 */ void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size); /* wbl reset for dm644x */ enum vpss_wbl_sel { VPSS_PCR_AEW_WBL_0 = 16, VPSS_PCR_AF_WBL_0, VPSS_PCR_RSZ4_WBL_0, VPSS_PCR_RSZ3_WBL_0, VPSS_PCR_RSZ2_WBL_0, VPSS_PCR_RSZ1_WBL_0, VPSS_PCR_PREV_WBL_0, VPSS_PCR_CCDC_WBL_O, }; /* clear wbl overflow flag for DM6446 */ int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel); /* set sync polarity*/ void vpss_set_sync_pol(struct vpss_sync_pol sync); /* set the PG_FRAME_SIZE register */ void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size); /* * vpss_check_and_clear_interrupt - check and clear interrupt * @irq - common enumerator for IRQ * * Following return values used:- * 0 - interrupt occurred and cleared * 1 - interrupt not occurred * 2 - interrupt status not available */ int vpss_dma_complete_interrupt(void); #endif PK ѹ�ZBGǝ� � Kconfignu �[��� PK ѹ�Z(]��� � � Makefilenu �[��� PK DJ�ZwqBb� � vpbe_venc.hnu �[��� PK DJ�Z���| | ccdc_types.hnu �[��� PK DJ�Z����� � � vpbe_types.hnu �[��� PK DJ�Z�c&a a � vpfe_capture.hnu �[��� PK DJ�Z\O�\� � �1 vpbe.hnu �[��� PK DJ�ZU��P� � �F vpfe_types.hnu �[��� PK DJ�Z}�p� � nI vpbe_display.hnu �[��� PK DJ�Z57f{ { @W dm355_ccdc.hnu �[��� PK DJ�Z� I�T T �s vpif_types.hnu �[��� PK DJ�Z, D��7 �7 �z isif.hnu �[��� PK DJ�Zٙ{6�& �& b� vpbe_osd.hnu �[��� PK DJ�Z���/ / G� dm644x_ccdc.hnu �[��� PK DJ�Z�'(�Y Y �� vpss.hnu �[��� PK [ B�
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