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usr/src/linux-headers-5.15.0-133/arch/sh/include/asm/hw_breakpoint.h��0000644��00000003662�15030301060�0020476 0��ustar�00��/* SPDX-License-Identifier: GPL-2.0 / #ifndef __ASM_SH_HW_BREAKPOINT_H #define __ASM_SH_HW_BREAKPOINT_H #include <uapi/asm/hw_breakpoint.h> #define __ARCH_HW_BREAKPOINT_H #include <linux/kdebug.h> #include <linux/types.h> struct arch_hw_breakpoint { unsigned long address; u16 len; u16 type; }; enum { SH_BREAKPOINT_READ = (1 << 1), SH_BREAKPOINT_WRITE = (1 << 2), SH_BREAKPOINT_RW = SH_BREAKPOINT_READ \| SH_BREAKPOINT_WRITE, SH_BREAKPOINT_LEN_1 = (1 << 12), SH_BREAKPOINT_LEN_2 = (1 << 13), SH_BREAKPOINT_LEN_4 = SH_BREAKPOINT_LEN_1 \| SH_BREAKPOINT_LEN_2, SH_BREAKPOINT_LEN_8 = (1 << 14), }; struct sh_ubc { const char name; unsigned int num_events; unsigned int trap_nr; void (enable)(struct arch_hw_breakpoint , int); void (disable)(struct arch_hw_breakpoint , int); void (enable_all)(unsigned long); void (disable_all)(void); unsigned long (active_mask)(void); unsigned long (triggered_mask)(void); void (clear_triggered_mask)(unsigned long); struct clk clk; /* optional interface clock / MSTP bit / }; struct perf_event_attr; struct perf_event; struct task_struct; struct pmu; / Maximum number of UBC channels / #define HBP_NUM 2 static inline int hw_breakpoint_slots(int type) { return HBP_NUM; } / arch/sh/kernel/hw_breakpoint.c / extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint hw); extern int hw_breakpoint_arch_parse(struct perf_event bp, const struct perf_event_attr attr, struct arch_hw_breakpoint hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block unused, unsigned long val, void data); int arch_install_hw_breakpoint(struct perf_event bp); void arch_uninstall_hw_breakpoint(struct perf_event bp); void hw_breakpoint_pmu_read(struct perf_event bp); extern void arch_fill_perf_breakpoint(struct perf_event bp); extern int register_sh_ubc(struct sh_ubc ); extern struct pmu perf_ops_bp; #endif /* __ASM_SH_HW_BREAKPOINT_H / ��usr/src/linux-headers-5.15.0-142/arch/sh/include/asm/hw_breakpoint.h��0000644��00000003662�15030423426�0020511 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __ASM_SH_HW_BREAKPOINT_H #define __ASM_SH_HW_BREAKPOINT_H #include <uapi/asm/hw_breakpoint.h> #define __ARCH_HW_BREAKPOINT_H #include <linux/kdebug.h> #include <linux/types.h> struct arch_hw_breakpoint { unsigned long address; u16 len; u16 type; }; enum { SH_BREAKPOINT_READ = (1 << 1), SH_BREAKPOINT_WRITE = (1 << 2), SH_BREAKPOINT_RW = SH_BREAKPOINT_READ \| SH_BREAKPOINT_WRITE, SH_BREAKPOINT_LEN_1 = (1 << 12), SH_BREAKPOINT_LEN_2 = (1 << 13), SH_BREAKPOINT_LEN_4 = SH_BREAKPOINT_LEN_1 \| SH_BREAKPOINT_LEN_2, SH_BREAKPOINT_LEN_8 = (1 << 14), }; struct sh_ubc { const char name; unsigned int num_events; unsigned int trap_nr; void (enable)(struct arch_hw_breakpoint , int); void (disable)(struct arch_hw_breakpoint , int); void (enable_all)(unsigned long); void (disable_all)(void); unsigned long (active_mask)(void); unsigned long (triggered_mask)(void); void (clear_triggered_mask)(unsigned long); struct clk clk; /* optional interface clock / MSTP bit / }; struct perf_event_attr; struct perf_event; struct task_struct; struct pmu; / Maximum number of UBC channels / #define HBP_NUM 2 static inline int hw_breakpoint_slots(int type) { return HBP_NUM; } / arch/sh/kernel/hw_breakpoint.c / extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint hw); extern int hw_breakpoint_arch_parse(struct perf_event bp, const struct perf_event_attr attr, struct arch_hw_breakpoint hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block unused, unsigned long val, void data); int arch_install_hw_breakpoint(struct perf_event bp); void arch_uninstall_hw_breakpoint(struct perf_event bp); void hw_breakpoint_pmu_read(struct perf_event bp); extern void arch_fill_perf_breakpoint(struct perf_event bp); extern int register_sh_ubc(struct sh_ubc ); extern struct pmu perf_ops_bp; #endif /* __ASM_SH_HW_BREAKPOINT_H / ��usr/src/linux-headers-5.15.0-141/arch/sh/include/asm/hw_breakpoint.h��0000644��00000003662�15030477053�0020515 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __ASM_SH_HW_BREAKPOINT_H #define __ASM_SH_HW_BREAKPOINT_H #include <uapi/asm/hw_breakpoint.h> #define __ARCH_HW_BREAKPOINT_H #include <linux/kdebug.h> #include <linux/types.h> struct arch_hw_breakpoint { unsigned long address; u16 len; u16 type; }; enum { SH_BREAKPOINT_READ = (1 << 1), SH_BREAKPOINT_WRITE = (1 << 2), SH_BREAKPOINT_RW = SH_BREAKPOINT_READ \| SH_BREAKPOINT_WRITE, SH_BREAKPOINT_LEN_1 = (1 << 12), SH_BREAKPOINT_LEN_2 = (1 << 13), SH_BREAKPOINT_LEN_4 = SH_BREAKPOINT_LEN_1 \| SH_BREAKPOINT_LEN_2, SH_BREAKPOINT_LEN_8 = (1 << 14), }; struct sh_ubc { const char name; unsigned int num_events; unsigned int trap_nr; void (enable)(struct arch_hw_breakpoint , int); void (disable)(struct arch_hw_breakpoint , int); void (enable_all)(unsigned long); void (disable_all)(void); unsigned long (active_mask)(void); unsigned long (triggered_mask)(void); void (clear_triggered_mask)(unsigned long); struct clk clk; /* optional interface clock / MSTP bit / }; struct perf_event_attr; struct perf_event; struct task_struct; struct pmu; / Maximum number of UBC channels / #define HBP_NUM 2 static inline int hw_breakpoint_slots(int type) { return HBP_NUM; } / arch/sh/kernel/hw_breakpoint.c / extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint hw); extern int hw_breakpoint_arch_parse(struct perf_event bp, const struct perf_event_attr attr, struct arch_hw_breakpoint hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block unused, unsigned long val, void data); int arch_install_hw_breakpoint(struct perf_event bp); void arch_uninstall_hw_breakpoint(struct perf_event bp); void hw_breakpoint_pmu_read(struct perf_event bp); extern void arch_fill_perf_breakpoint(struct perf_event bp); extern int register_sh_ubc(struct sh_ubc ); extern struct pmu perf_ops_bp; #endif /* __ASM_SH_HW_BREAKPOINT_H / ��usr/src/linux-headers-5.15.0-133/arch/arm64/include/asm/hw_breakpoint.h��0000644��00000007773�15030520664�0021041 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0-only / / * Copyright (C) 2012 ARM Ltd. / #ifndef __ASM_HW_BREAKPOINT_H #define __ASM_HW_BREAKPOINT_H #include <asm/cputype.h> #include <asm/cpufeature.h> #include <asm/sysreg.h> #include <asm/virt.h> struct arch_hw_breakpoint_ctrl { u32 __reserved : 19, len : 8, type : 2, privilege : 2, enabled : 1; }; struct arch_hw_breakpoint { u64 address; u64 trigger; struct arch_hw_breakpoint_ctrl ctrl; }; / Privilege Levels / #define AARCH64_BREAKPOINT_EL1 1 #define AARCH64_BREAKPOINT_EL0 2 #define DBG_HMC_HYP (1 << 13) static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) { u32 val = (ctrl.len << 5) \| (ctrl.type << 3) \| (ctrl.privilege << 1) \| ctrl.enabled; if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1) val \|= DBG_HMC_HYP; return val; } static inline void decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl ctrl) { ctrl->enabled = reg & 0x1; reg >>= 1; ctrl->privilege = reg & 0x3; reg >>= 2; ctrl->type = reg & 0x3; reg >>= 2; ctrl->len = reg & 0xff; } /* Breakpoint / #define ARM_BREAKPOINT_EXECUTE 0 / Watchpoints / #define ARM_BREAKPOINT_LOAD 1 #define ARM_BREAKPOINT_STORE 2 #define AARCH64_ESR_ACCESS_MASK (1 << 6) / Lengths / #define ARM_BREAKPOINT_LEN_1 0x1 #define ARM_BREAKPOINT_LEN_2 0x3 #define ARM_BREAKPOINT_LEN_3 0x7 #define ARM_BREAKPOINT_LEN_4 0xf #define ARM_BREAKPOINT_LEN_5 0x1f #define ARM_BREAKPOINT_LEN_6 0x3f #define ARM_BREAKPOINT_LEN_7 0x7f #define ARM_BREAKPOINT_LEN_8 0xff / Kernel stepping / #define ARM_KERNEL_STEP_NONE 0 #define ARM_KERNEL_STEP_ACTIVE 1 #define ARM_KERNEL_STEP_SUSPEND 2 / * Limits. * Changing these will require modifications to the register accessors. / #define ARM_MAX_BRP 16 #define ARM_MAX_WRP 16 / Virtual debug register bases. / #define AARCH64_DBG_REG_BVR 0 #define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP) #define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP) #define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP) / Debug register names. / #define AARCH64_DBG_REG_NAME_BVR bvr #define AARCH64_DBG_REG_NAME_BCR bcr #define AARCH64_DBG_REG_NAME_WVR wvr #define AARCH64_DBG_REG_NAME_WCR wcr / Accessor macros for the debug registers. / #define AARCH64_DBG_READ(N, REG, VAL) do {\ VAL = read_sysreg(dbg##REG##N##_el1);\ } while (0) #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ write_sysreg(VAL, dbg##REG##N##_el1);\ } while (0) struct task_struct; struct notifier_block; struct perf_event_attr; struct perf_event; struct pmu; extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, int gen_len, int gen_type, int offset); extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint hw); extern int hw_breakpoint_arch_parse(struct perf_event bp, const struct perf_event_attr attr, struct arch_hw_breakpoint hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block unused, unsigned long val, void data); extern int arch_install_hw_breakpoint(struct perf_event bp); extern void arch_uninstall_hw_breakpoint(struct perf_event bp); extern void hw_breakpoint_pmu_read(struct perf_event bp); extern int hw_breakpoint_slots(int type); #ifdef CONFIG_HAVE_HW_BREAKPOINT extern void hw_breakpoint_thread_switch(struct task_struct next); extern void ptrace_hw_copy_thread(struct task_struct task); #else static inline void hw_breakpoint_thread_switch(struct task_struct next) { } static inline void ptrace_hw_copy_thread(struct task_struct task) { } #endif / Determine number of BRP registers available. / static inline int get_num_brps(void) { u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); return 1 + cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_BRPS_SHIFT); } / Determine number of WRP registers available. / static inline int get_num_wrps(void) { u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); return 1 + cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_WRPS_SHIFT); } #endif / __ASM_BREAKPOINT_H / ��usr/src/linux-headers-5.15.0-142/arch/arm/include/asm/hw_breakpoint.h��0000644��00000007343�15030567611�0020663 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / #ifndef _ARM_HW_BREAKPOINT_H #define _ARM_HW_BREAKPOINT_H #ifdef __KERNEL__ struct task_struct; #ifdef CONFIG_HAVE_HW_BREAKPOINT struct arch_hw_breakpoint_ctrl { u32 __reserved : 9, mismatch : 1, : 9, len : 8, type : 2, privilege : 2, enabled : 1; }; struct arch_hw_breakpoint { u32 address; u32 trigger; struct arch_hw_breakpoint_ctrl step_ctrl; struct arch_hw_breakpoint_ctrl ctrl; }; static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) { return (ctrl.mismatch << 22) \| (ctrl.len << 5) \| (ctrl.type << 3) \| (ctrl.privilege << 1) \| ctrl.enabled; } static inline void decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl ctrl) { ctrl->enabled = reg & 0x1; reg >>= 1; ctrl->privilege = reg & 0x3; reg >>= 2; ctrl->type = reg & 0x3; reg >>= 2; ctrl->len = reg & 0xff; reg >>= 17; ctrl->mismatch = reg & 0x1; } /* Debug architecture numbers. / #define ARM_DEBUG_ARCH_RESERVED 0 / In case of ptrace ABI updates. / #define ARM_DEBUG_ARCH_V6 1 #define ARM_DEBUG_ARCH_V6_1 2 #define ARM_DEBUG_ARCH_V7_ECP14 3 #define ARM_DEBUG_ARCH_V7_MM 4 #define ARM_DEBUG_ARCH_V7_1 5 #define ARM_DEBUG_ARCH_V8 6 #define ARM_DEBUG_ARCH_V8_1 7 #define ARM_DEBUG_ARCH_V8_2 8 #define ARM_DEBUG_ARCH_V8_4 9 / Breakpoint / #define ARM_BREAKPOINT_EXECUTE 0 / Watchpoints / #define ARM_BREAKPOINT_LOAD 1 #define ARM_BREAKPOINT_STORE 2 #define ARM_FSR_ACCESS_MASK (1 << 11) / Privilege Levels / #define ARM_BREAKPOINT_PRIV 1 #define ARM_BREAKPOINT_USER 2 / Lengths / #define ARM_BREAKPOINT_LEN_1 0x1 #define ARM_BREAKPOINT_LEN_2 0x3 #define ARM_BREAKPOINT_LEN_4 0xf #define ARM_BREAKPOINT_LEN_8 0xff / Limits / #define ARM_MAX_BRP 16 #define ARM_MAX_WRP 16 #define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP) / DSCR method of entry bits. / #define ARM_DSCR_MOE(x) ((x >> 2) & 0xf) #define ARM_ENTRY_BREAKPOINT 0x1 #define ARM_ENTRY_ASYNC_WATCHPOINT 0x2 #define ARM_ENTRY_SYNC_WATCHPOINT 0xa / DSCR monitor/halting bits. / #define ARM_DSCR_HDBGEN (1 << 14) #define ARM_DSCR_MDBGEN (1 << 15) / OSLSR os lock model bits / #define ARM_OSLSR_OSLM0 (1 << 0) / opcode2 numbers for the co-processor instructions. / #define ARM_OP2_BVR 4 #define ARM_OP2_BCR 5 #define ARM_OP2_WVR 6 #define ARM_OP2_WCR 7 / Base register numbers for the debug registers. / #define ARM_BASE_BVR 64 #define ARM_BASE_BCR 80 #define ARM_BASE_WVR 96 #define ARM_BASE_WCR 112 / Accessor macros for the debug registers. / #define ARM_DBG_READ(N, M, OP2, VAL) do {\ asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\ } while (0) #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\ } while (0) struct perf_event_attr; struct notifier_block; struct perf_event; struct pmu; extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, int gen_len, int gen_type); extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint hw); extern int hw_breakpoint_arch_parse(struct perf_event bp, const struct perf_event_attr attr, struct arch_hw_breakpoint hw); extern int hw_breakpoint_exceptions_notify(struct notifier_block unused, unsigned long val, void data); extern u8 arch_get_debug_arch(void); extern u8 arch_get_max_wp_len(void); extern void clear_ptrace_hw_breakpoint(struct task_struct tsk); int arch_install_hw_breakpoint(struct perf_event bp); void arch_uninstall_hw_breakpoint(struct perf_event bp); void hw_breakpoint_pmu_read(struct perf_event bp); int hw_breakpoint_slots(int type); #else static inline void clear_ptrace_hw_breakpoint(struct task_struct tsk) {} #endif /* CONFIG_HAVE_HW_BREAKPOINT / #endif / __KERNEL__ / #endif / _ARM_HW_BREAKPOINT_H */ ��

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