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usr/src/linux-headers-5.15.0-133/arch/arm/mach-rpc/include/mach/io.h��0000644��00000001240�15030355373�0020246 0��ustar�00��/* SPDX-License-Identifier: GPL-2.0-only / / * arch/arm/mach-rpc/include/mach/io.h * * Copyright (C) 1997 Russell King * * Modifications: * 06-Dec-1997 RMK Created. / #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H #include <mach/hardware.h> #define IO_SPACE_LIMIT 0xffff / * We need PC style IO addressing for: * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7) * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a) * - 8250 serial (only for compile) * * These peripherals are found in an area of MMIO which looks very much * like an ISA bus, but with registers at the low byte of each word. / #define __io(a) (PCIO_BASE + ((a) << 2)) #endif ��usr/src/linux-headers-5.15.0-142/arch/arc/include/asm/io.h��0000644��00000014223�15030376044�0016415 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0-only / / * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) / #ifndef _ASM_ARC_IO_H #define _ASM_ARC_IO_H #include <linux/types.h> #include <asm/byteorder.h> #include <asm/page.h> #include <asm/unaligned.h> #ifdef CONFIG_ISA_ARCV2 #include <asm/barrier.h> #define __iormb() rmb() #define __iowmb() wmb() #else #define __iormb() do { } while (0) #define __iowmb() do { } while (0) #endif extern void __iomem ioremap(phys_addr_t paddr, unsigned long size); extern void __iomem ioremap_prot(phys_addr_t paddr, unsigned long size, unsigned long flags); static inline void __iomem ioport_map(unsigned long port, unsigned int nr) { return (void __iomem )port; } static inline void ioport_unmap(void __iomem addr) { } extern void iounmap(const volatile void __iomem addr); / * io{read,write}{16,32}be() macros / #define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) #define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); }) #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); }) / Change struct page to physical address / #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) #define __raw_readb __raw_readb static inline u8 __raw_readb(const volatile void __iomem addr) { u8 b; __asm__ __volatile__( " ldb%U1 %0, %1 \n" : "=r" (b) : "m" ((volatile u8 __force )addr) : "memory"); return b; } #define __raw_readw __raw_readw static inline u16 __raw_readw(const volatile void __iomem addr) { u16 s; __asm__ __volatile__( " ldw%U1 %0, %1 \n" : "=r" (s) : "m" ((volatile u16 __force )addr) : "memory"); return s; } #define __raw_readl __raw_readl static inline u32 __raw_readl(const volatile void __iomem addr) { u32 w; __asm__ __volatile__( " ld%U1 %0, %1 \n" : "=r" (w) : "m" ((volatile u32 __force )addr) : "memory"); return w; } /* * {read,write}s{b,w,l}() repeatedly access the same IO address in * native endianness in 8-, 16-, 32-bit chunks {into,from} memory, * @count times / #define __raw_readsx(t,f) \ static inline void __raw_reads##f(const volatile void __iomem addr, \ void ptr, unsigned int count) \ { \ bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ u##t buf = ptr; \ \ if (!count) \ return; \ \ /* Some ARC CPU's don't support unaligned accesses / \ if (is_aligned) { \ do { \ u##t x = __raw_read##f(addr); \ buf++ = x; \ } while (--count); \ } else { \ do { \ u##t x = __raw_read##f(addr); \ put_unaligned(x, buf++); \ } while (--count); \ } \ } #define __raw_readsb __raw_readsb __raw_readsx(8, b) #define __raw_readsw __raw_readsw __raw_readsx(16, w) #define __raw_readsl __raw_readsl __raw_readsx(32, l) #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem addr) { __asm__ __volatile__( " stb%U1 %0, %1 \n" : : "r" (b), "m" ((volatile u8 __force )addr) : "memory"); } #define __raw_writew __raw_writew static inline void __raw_writew(u16 s, volatile void __iomem addr) { __asm__ __volatile__( " stw%U1 %0, %1 \n" : : "r" (s), "m" ((volatile u16 __force )addr) : "memory"); } #define __raw_writel __raw_writel static inline void __raw_writel(u32 w, volatile void __iomem addr) { __asm__ __volatile__( " st%U1 %0, %1 \n" : : "r" (w), "m" ((volatile u32 __force )addr) : "memory"); } #define __raw_writesx(t,f) \ static inline void __raw_writes##f(volatile void __iomem addr, \ const void ptr, unsigned int count) \ { \ bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ const u##t buf = ptr; \ \ if (!count) \ return; \ \ /* Some ARC CPU's don't support unaligned accesses / \ if (is_aligned) { \ do { \ __raw_write##f(buf++, addr); \ } while (--count); \ } else { \ do { \ __raw_write##f(get_unaligned(buf++), addr); \ } while (--count); \ } \ } #define __raw_writesb __raw_writesb __raw_writesx(8, b) #define __raw_writesw __raw_writesw __raw_writesx(16, w) #define __raw_writesl __raw_writesl __raw_writesx(32, l) /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed * Based on ARM model for the typical use case * * <ST [DMA buffer]> * <writel MMIO "go" reg> * or: * <readl MMIO "status" reg> * <LD [DMA buffer]> * * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com / #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) #define readsb(p,d,l) ({ __raw_readsb(p,d,l); __iormb(); }) #define readsw(p,d,l) ({ __raw_readsw(p,d,l); __iormb(); }) #define readsl(p,d,l) ({ __raw_readsl(p,d,l); __iormb(); }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) #define writesb(p,d,l) ({ __iowmb(); __raw_writesb(p,d,l); }) #define writesw(p,d,l) ({ __iowmb(); __raw_writesw(p,d,l); }) #define writesl(p,d,l) ({ __iowmb(); __raw_writesl(p,d,l); }) / * Relaxed API for drivers which can handle barrier ordering themselves * * Also these are defined to perform little endian accesses. * To provide the typical device register semantics of fixed endian, * swap the byte order for Big Endian * * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de / #define readb_relaxed(c) __raw_readb(c) #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) #include <asm-generic/io.h> #endif / _ASM_ARC_IO_H / ��usr/src/linux-headers-5.15.0-133/arch/mips/include/asm/sn/io.h��0000644��00000003514�15030520655�0017240 0��ustar�00��/ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2000, 2003 Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. / #ifndef _ASM_SN_IO_H #define _ASM_SN_IO_H #if defined(CONFIG_SGI_IP27) #include <asm/sn/sn0/hubio.h> #endif #define IIO_ITTE_BASE 0x400160 / base of translation table entries / #define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8(bigwin)) #define IIO_ITTE_OFFSET_BITS 5 /* size of offset field / #define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1) #define IIO_ITTE_OFFSET_SHIFT 0 #define IIO_ITTE_WIDGET_BITS 4 / size of widget field / #define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1) #define IIO_ITTE_WIDGET_SHIFT 8 #define IIO_ITTE_IOSP 1 / I/O Space bit / #define IIO_ITTE_IOSP_MASK 1 #define IIO_ITTE_IOSP_SHIFT 12 #define HUB_PIO_MAP_TO_MEM 0 #define HUB_PIO_MAP_TO_IO 1 #define IIO_ITTE_INVALID_WIDGET 3 / an invalid widget / #define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \ REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \ (((((addr) >> BWIN_SIZE_BITS) & \ IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) \| \ (io_or_mem << IIO_ITTE_IOSP_SHIFT) \| \ (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT))) #define IIO_ITTE_DISABLE(nasid, bigwin) \ IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \ (bigwin), IIO_ITTE_INVALID_WIDGET, 0) #define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_PTR((nasid), IIO_ITTE(bigwin)) / * Macro which takes the widget number, and returns the * IO PRB address of that widget. * value _x is expected to be a widget number in the range * 0, 8 - 0xF / #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ (_x) : \ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) #endif / _ASM_SN_IO_H / ��usr/src/linux-headers-5.15.0-142/arch/mips/include/asm/io.h��0000644��00000041666�15030521132�0016621 0��ustar�00��/ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994, 1995 Waldorf GmbH * Copyright (C) 1994 - 2000, 06 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. * Author: Maciej W. Rozycki <macro@mips.com> / #ifndef _ASM_IO_H #define _ASM_IO_H #define ARCH_HAS_IOREMAP_WC #include <linux/compiler.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/irqflags.h> #include <asm/addrspace.h> #include <asm/barrier.h> #include <asm/bug.h> #include <asm/byteorder.h> #include <asm/cpu.h> #include <asm/cpu-features.h> #include <asm-generic/iomap.h> #include <asm/page.h> #include <asm/pgtable-bits.h> #include <asm/processor.h> #include <asm/string.h> #include <mangle-port.h> / * Raw operations are never swapped in software. OTOH values that raw * operations are working on may or may not have been swapped by the bus * hardware. An example use would be for flash memory that's used for * execute in place. / # define __raw_ioswabb(a, x) (x) # define __raw_ioswabw(a, x) (x) # define __raw_ioswabl(a, x) (x) # define __raw_ioswabq(a, x) (x) # define ____raw_ioswabq(a, x) (x) # define __relaxed_ioswabb ioswabb # define __relaxed_ioswabw ioswabw # define __relaxed_ioswabl ioswabl # define __relaxed_ioswabq ioswabq / ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h / / * On MIPS I/O ports are memory mapped, so we access them using normal * load/store instructions. mips_io_port_base is the virtual address to * which all ports are being mapped. For sake of efficiency some code * assumes that this is an address that can be loaded with a single lui * instruction, so the lower 16 bits must be zero. Should be true on * any sane architecture; generic code does not use this assumption. / extern unsigned long mips_io_port_base; static inline void set_io_port_base(unsigned long base) { mips_io_port_base = base; } / * Provide the necessary definitions for generic iomap. We make use of * mips_io_port_base for iomap(), but we don't reserve any low addresses for * use with I/O ports. / #define HAVE_ARCH_PIO_SIZE #define PIO_OFFSET mips_io_port_base #define PIO_MASK IO_SPACE_LIMIT #define PIO_RESERVED 0x0UL / * Enforce in-order execution of data I/O. In the MIPS architecture * these are equivalent to corresponding platform-specific memory * barriers defined in <asm/barrier.h>. API pinched from PowerPC, * with sync additionally defined. / #define iobarrier_rw() mb() #define iobarrier_r() rmb() #define iobarrier_w() wmb() #define iobarrier_sync() iob() / * virt_to_phys - map virtual addresses to physical * @address: address to remap * * The returned physical address is the physical (CPU) mapping for * the memory address given. It is only valid to use this function on * addresses directly mapped or allocated via kmalloc. * * This function does not give bus mappings for DMA transfers. In * almost all conceivable cases a device driver should not be using * this function / static inline unsigned long __virt_to_phys_nodebug(volatile const void address) { return __pa(address); } #ifdef CONFIG_DEBUG_VIRTUAL extern phys_addr_t __virt_to_phys(volatile const void x); #else #define __virt_to_phys(x) __virt_to_phys_nodebug(x) #endif #define virt_to_phys virt_to_phys static inline phys_addr_t virt_to_phys(const volatile void x) { return __virt_to_phys(x); } /* * phys_to_virt - map physical address to virtual * @address: address to remap * * The returned virtual address is a current CPU mapping for * the memory address given. It is only valid to use this function on * addresses that have a kernel mapping * * This function does not handle bus mappings for DMA transfers. In * almost all conceivable cases a device driver should not be using * this function / static inline void phys_to_virt(unsigned long address) { return (void )(address + PAGE_OFFSET - PHYS_OFFSET); } / * ISA I/O bus memory addresses are 1:1 with the physical address. / static inline unsigned long isa_virt_to_bus(volatile void address) { return virt_to_phys(address); } static inline void isa_bus_to_virt(unsigned long address) { return phys_to_virt(address); } / * However PCI ones are not necessarily 1:1 and therefore these interfaces * are forbidden in portable PCI drivers. * * Allow them for x86 for legacy drivers, though. / #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt / * Change "struct page" to physical address. / #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) void __iomem ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long prot_val); void iounmap(const volatile void __iomem addr); / * ioremap - map bus memory into CPU space * @offset: bus address of the memory * @size: size of the resource to map * * ioremap performs a platform specific sequence of operations to * make bus memory CPU accessible via the readb/readw/readl/writeb/ * writew/writel functions and the other mmio helpers. The returned * address is not guaranteed to be usable directly as a virtual * address. / #define ioremap(offset, size) \ ioremap_prot((offset), (size), _CACHE_UNCACHED) #define ioremap_uc ioremap / * ioremap_cache - map bus memory into CPU space * @offset: bus address of the memory * @size: size of the resource to map * * ioremap_cache performs a platform specific sequence of operations to * make bus memory CPU accessible via the readb/readw/readl/writeb/ * writew/writel functions and the other mmio helpers. The returned * address is not guaranteed to be usable directly as a virtual * address. * * This version of ioremap ensures that the memory is marked cachable by * the CPU. Also enables full write-combining. Useful for some * memory-like regions on I/O busses. / #define ioremap_cache(offset, size) \ ioremap_prot((offset), (size), _page_cachable_default) / * ioremap_wc - map bus memory into CPU space * @offset: bus address of the memory * @size: size of the resource to map * * ioremap_wc performs a platform specific sequence of operations to * make bus memory CPU accessible via the readb/readw/readl/writeb/ * writew/writel functions and the other mmio helpers. The returned * address is not guaranteed to be usable directly as a virtual * address. * * This version of ioremap ensures that the memory is marked uncachable * but accelerated by means of write-combining feature. It is specifically * useful for PCIe prefetchable windows, which may vastly improve a * communications performance. If it was determined on boot stage, what * CPU CCA doesn't support UCA, the method shall fall-back to the * _CACHE_UNCACHED option (see cpu_probe() method). / #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) #if defined(CONFIG_CPU_CAVIUM_OCTEON) \|\| defined(CONFIG_CPU_LOONGSON64) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier() #endif #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ \ static inline void pfx##write##bwlq(type val, \ volatile void __iomem mem) \ { \ volatile type __mem; \ type __val; \ \ if (barrier) \ iobarrier_rw(); \ else \ war_io_reorder_wmb(); \ \ __mem = (void )__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ __val = pfx##ioswab##bwlq(__mem, val); \ \ if (sizeof(type) != sizeof(u64) \|\| sizeof(u64) == sizeof(long)) \ __mem = __val; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ type __tmp; \ \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set push" "\t\t# __writeq""\n\t" \ ".set arch=r4000" "\n\t" \ "dsll32 %L0, %L0, 0" "\n\t" \ "dsrl32 %L0, %L0, 0" "\n\t" \ "dsll32 %M0, %M0, 0" "\n\t" \ "or %L0, %L0, %M0" "\n\t" \ "sd %L0, %2" "\n\t" \ ".set pop" "\n" \ : "=r" (__tmp) \ : "0" (__val), "m" (__mem)); \ if (irq) \ local_irq_restore(__flags); \ } else \ BUG(); \ } \ \ static inline type pfx##read##bwlq(const volatile void __iomem mem) \ { \ volatile type __mem; \ type __val; \ \ __mem = (void )__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ if (barrier) \ iobarrier_rw(); \ \ if (sizeof(type) != sizeof(u64) \|\| sizeof(u64) == sizeof(long)) \ __val = __mem; \ else if (cpu_has_64bits) { \ unsigned long __flags; \ \ if (irq) \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set push" "\t\t# __readq" "\n\t" \ ".set arch=r4000" "\n\t" \ "ld %L0, %1" "\n\t" \ "dsra32 %M0, %L0, 0" "\n\t" \ "sll %L0, %L0, 0" "\n\t" \ ".set pop" "\n" \ : "=r" (__val) \ : "m" (__mem)); \ if (irq) \ local_irq_restore(__flags); \ } else { \ __val = 0; \ BUG(); \ } \ \ / prevent prefetching of coherent DMA data prematurely / \ if (!relax) \ rmb(); \ return pfx##ioswab##bwlq(__mem, __val); \ } #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ \ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ { \ volatile type __addr; \ type __val; \ \ if (barrier) \ iobarrier_rw(); \ else \ war_io_reorder_wmb(); \ \ __addr = (void )__swizzle_addr_##bwlq(mips_io_port_base + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ \ / Really, we want this to be atomic / \ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ \ __addr = __val; \ } \ \ static inline type pfx##in##bwlq##p(unsigned long port) \ { \ volatile type __addr; \ type __val; \ \ __addr = (void )__swizzle_addr_##bwlq(mips_io_port_base + port); \ \ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ \ if (barrier) \ iobarrier_rw(); \ \ __val = __addr; \ \ / prevent prefetching of coherent DMA data prematurely / \ if (!relax) \ rmb(); \ return pfx##ioswab##bwlq(__addr, __val); \ } #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \ \ __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1) #define BUILDIO_MEM(bwlq, type) \ \ __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \ __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \ __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \ __BUILD_MEMORY_PFX(, bwlq, type, 0) BUILDIO_MEM(b, u8) BUILDIO_MEM(w, u16) BUILDIO_MEM(l, u32) #ifdef CONFIG_64BIT BUILDIO_MEM(q, u64) #else __BUILD_MEMORY_PFX(__raw_, q, u64, 0) __BUILD_MEMORY_PFX(__mem_, q, u64, 0) #endif #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) #define BUILDIO_IOPORT(bwlq, type) \ __BUILD_IOPORT_PFX(, bwlq, type) \ __BUILD_IOPORT_PFX(__mem_, bwlq, type) BUILDIO_IOPORT(b, u8) BUILDIO_IOPORT(w, u16) BUILDIO_IOPORT(l, u32) #ifdef CONFIG_64BIT BUILDIO_IOPORT(q, u64) #endif #define __BUILDIO(bwlq, type) \ \ __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0) __BUILDIO(q, u64) #define readb_relaxed __relaxed_readb #define readw_relaxed __relaxed_readw #define readl_relaxed __relaxed_readl #ifdef CONFIG_64BIT #define readq_relaxed __relaxed_readq #endif #define writeb_relaxed __relaxed_writeb #define writew_relaxed __relaxed_writew #define writel_relaxed __relaxed_writel #ifdef CONFIG_64BIT #define writeq_relaxed __relaxed_writeq #endif #define readb_be(addr) \ __raw_readb((__force unsigned )(addr)) #define readw_be(addr) \ be16_to_cpu(__raw_readw((__force unsigned )(addr))) #define readl_be(addr) \ be32_to_cpu(__raw_readl((__force unsigned )(addr))) #define readq_be(addr) \ be64_to_cpu(__raw_readq((__force unsigned )(addr))) #define writeb_be(val, addr) \ __raw_writeb((val), (__force unsigned )(addr)) #define writew_be(val, addr) \ __raw_writew(cpu_to_be16((val)), (__force unsigned )(addr)) #define writel_be(val, addr) \ __raw_writel(cpu_to_be32((val)), (__force unsigned )(addr)) #define writeq_be(val, addr) \ __raw_writeq(cpu_to_be64((val)), (__force unsigned )(addr)) / * Some code tests for these symbols / #ifdef CONFIG_64BIT #define readq readq #define writeq writeq #endif #define __BUILD_MEMORY_STRING(bwlq, type) \ \ static inline void writes##bwlq(volatile void __iomem mem, \ const void addr, unsigned int count) \ { \ const volatile type __addr = addr; \ \ while (count--) { \ __mem_write##bwlq(__addr, mem); \ __addr++; \ } \ } \ \ static inline void reads##bwlq(volatile void __iomem mem, void addr, \ unsigned int count) \ { \ volatile type __addr = addr; \ \ while (count--) { \ __addr = __mem_read##bwlq(mem); \ __addr++; \ } \ } #define __BUILD_IOPORT_STRING(bwlq, type) \ \ static inline void outs##bwlq(unsigned long port, const void addr, \ unsigned int count) \ { \ const volatile type __addr = addr; \ \ while (count--) { \ __mem_out##bwlq(__addr, port); \ __addr++; \ } \ } \ \ static inline void ins##bwlq(unsigned long port, void addr, \ unsigned int count) \ { \ volatile type __addr = addr; \ \ while (count--) { \ __addr = __mem_in##bwlq(port); \ __addr++; \ } \ } #define BUILDSTRING(bwlq, type) \ \ __BUILD_MEMORY_STRING(bwlq, type) \ __BUILD_IOPORT_STRING(bwlq, type) BUILDSTRING(b, u8) BUILDSTRING(w, u16) BUILDSTRING(l, u32) #ifdef CONFIG_64BIT BUILDSTRING(q, u64) #endif static inline void memset_io(volatile void __iomem addr, unsigned char val, int count) { memset((void __force ) addr, val, count); } static inline void memcpy_fromio(void dst, const volatile void __iomem src, int count) { memcpy(dst, (void __force ) src, count); } static inline void memcpy_toio(volatile void __iomem dst, const void src, int count) { memcpy((void __force ) dst, src, count); } / * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that * can be applied to dma buffers. * * - dma_cache_wback_inv(start, size) makes caches and coherent by * writing the content of the caches back to memory, if necessary. * The function also invalidates the affected part of the caches as * necessary before DMA transfers from outside to memory. * - dma_cache_wback(start, size) makes caches and coherent by * writing the content of the caches back to memory, if necessary. * The function also invalidates the affected part of the caches as * necessary before DMA transfers from outside to memory. * - dma_cache_inv(start, size) invalidates the affected parts of the * caches. Dirty lines of the caches may be written back or simply * be discarded. This operation is necessary before dma operations * to the memory. * * This API used to be exported; it now is for arch code internal use only. / #ifdef CONFIG_DMA_NONCOHERENT extern void (_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (_dma_cache_wback)(unsigned long start, unsigned long size); extern void (_dma_cache_inv)(unsigned long start, unsigned long size); #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) #define dma_cache_wback(start, size) _dma_cache_wback(start, size) #define dma_cache_inv(start, size) _dma_cache_inv(start, size) #else /* Sane hardware / #define dma_cache_wback_inv(start,size) \ do { (void) (start); (void) (size); } while (0) #define dma_cache_wback(start,size) \ do { (void) (start); (void) (size); } while (0) #define dma_cache_inv(start,size) \ do { (void) (start); (void) (size); } while (0) #endif / CONFIG_DMA_NONCOHERENT / / * Read a 32-bit register that requires a 64-bit read cycle on the bus. * Avoid interrupt mucking, just adjust the address for 4-byte access. * Assume the addresses are 8-byte aligned. / #ifdef __MIPSEB__ #define __CSR_32_ADJUST 4 #else #define __CSR_32_ADJUST 0 #endif #define csr_out32(v, a) ((volatile u32 )((unsigned long)(a) + __CSR_32_ADJUST) = (v)) #define csr_in32(a) ((volatile u32 )((unsigned long)(a) + __CSR_32_ADJUST)) / * Convert a physical pointer to a virtual kernel pointer for /dev/mem * access / #define xlate_dev_mem_ptr(p) __va(p) void __ioread64_copy(void to, const void __iomem from, size_t count); #endif / _ASM_IO_H / ��usr/src/linux-headers-5.15.0-133/arch/nios2/include/asm/io.h��0000644��00000002446�15030543273�0016706 0��ustar�00��/ * Copyright (C) 2014 Altera Corporation * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch> * Copyright (C) 2004 Microtronix Datacom Ltd. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. / #ifndef _ASM_NIOS2_IO_H #define _ASM_NIOS2_IO_H #include <linux/types.h> #include <asm/pgtable-bits.h> / PCI is not supported in nios2, set this to 0. / #define IO_SPACE_LIMIT 0 #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) #define readl_relaxed(addr) readl(addr) #define writeb_relaxed(x, addr) writeb(x, addr) #define writew_relaxed(x, addr) writew(x, addr) #define writel_relaxed(x, addr) writel(x, addr) void __iomem ioremap(unsigned long physaddr, unsigned long size); void iounmap(void __iomem addr); / Pages to physical address... / #define page_to_phys(page) virt_to_phys(page_to_virt(page)) / Macros used for converting between virtual and physical mappings. / #define phys_to_virt(vaddr) \ ((void )((unsigned long)(vaddr) \| CONFIG_NIOS2_KERNEL_REGION_BASE)) /* Clear top 3 bits / #define virt_to_phys(vaddr) \ ((unsigned long)((unsigned long)(vaddr) & ~0xE0000000)) #include <asm-generic/io.h> #endif / _ASM_NIOS2_IO_H / ��usr/src/linux-headers-5.15.0-133/arch/microblaze/include/asm/io.h��0000644��00000003233�15030566132�0017775 0��ustar�00��/ SPDX-License-Identifier: GPL-2.0 / / * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> * Copyright (C) 2007-2009 PetaLogix * Copyright (C) 2006 Atmark Techno, Inc. / #ifndef _ASM_MICROBLAZE_IO_H #define _ASM_MICROBLAZE_IO_H #include <asm/byteorder.h> #include <asm/page.h> #include <linux/types.h> #include <linux/mm.h> / Get struct page {...} / #ifndef CONFIG_PCI #define _IO_BASE 0 #define _ISA_MEM_BASE 0 #else #define _IO_BASE isa_io_base #define _ISA_MEM_BASE isa_mem_base struct pci_dev; extern void pci_iounmap(struct pci_dev dev, void __iomem ); #define pci_iounmap pci_iounmap extern unsigned long isa_io_base; extern resource_size_t isa_mem_base; #endif #define PCI_IOBASE ((void __iomem )_IO_BASE) #define IO_SPACE_LIMIT (0xFFFFFFFF) #define page_to_bus(page) (page_to_phys(page)) extern void iounmap(volatile void __iomem addr); extern void __iomem ioremap(phys_addr_t address, unsigned long size); /* Big Endian / #define out_be32(a, v) __raw_writel((v), (void __iomem __force )(a)) #define out_be16(a, v) __raw_writew((v), (a)) #define in_be32(a) __raw_readl((const void __iomem __force )(a)) #define in_be16(a) __raw_readw(a) #define writel_be(v, a) out_be32((__force unsigned )a, v) #define readl_be(a) in_be32((__force unsigned )a) / Little endian / #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a)) #define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a)) #define in_le32(a) __le32_to_cpu(__raw_readl(a)) #define in_le16(a) __le16_to_cpu(__raw_readw(a)) / Byte ops / #define out_8(a, v) __raw_writeb((v), (a)) #define in_8(a) __raw_readb(a) #include <asm-generic/io.h> #endif / _ASM_MICROBLAZE_IO_H */ ��

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