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PK �Z��M1E 1E irq-madera.konu �[��� ELF > 9 @ @ % $ GNU �_ `�]������J�҈ Linux Linux � UH��SH�G@H�Xxf���X � H�]�1��� H��H H�� H�� � ��f � � UH��SH�G@H�Xxf���X � H�]�1��� H��H H�� H�� � ��f � � UH��SH�G@H�Xxf���X � H�]�1��� H��H H�� H�� � ��f � � UH��SH�G@H�Xxf���X � H�]�1��� H��H H�� H�� � ��f � � UH�GPH�@xH��H��P ��X HǀH � 1�]� f. � � UH��ATSH��H�GPH�Xx D ��� L�g���� �� H�;�t"j � E1�E1�1ɾ� � Z��� ��X H�;1ɺ L��P I� � ��� L��H H�e�[A\]� L�gH�� H�� L��� ��� ���h�����X � H��� H�@� ���v����@�����X H�� L��� ���� ��H�� L��E�� �E�� ��H�� L��E�� �E�� H�� L��� ���� � UH�� H�� H��� ]� UH�� H��� ]� No IRQ resume, disabling IRQ Suspend, disabling IRQ Resume, reenabling IRQ probe Invalid IRQ: %d add_irq_chip failed: %d madera-irq irq_madera drivers/irqchip/irq-madera.c madera IRQ No IRQ suspend, reenabling IRQ Host interrupt not level-triggered Failed to set IRQ polarity: %d madera_irq_probe madera_suspend madera_resume madera_suspend_noirq madera_resume_noirq A � H @ � @ � @ license=GPL v2 author=Richard Fitzgerald <rf@opensource.cirrus.com> description=Madera IRQ driver softdep=pre: madera srcversion=9A71CFB2766EE2C76FA9206 depends= retpoline=Y intree=Y name=irq_madera vermagic=5.15.0-141-generic SMP mod_unload modversions �na� module_layout N4<p platform_driver_unregister V�� __platform_driver_register �L�{ _dev_err q�E� irq_get_irq_data Х�� regmap_add_irq_chip �i�P regmap_update_bits_base �^ regmap_del_irq_chip � � enable_irq �L� __dynamic_dev_dbg �9�[ __x86_return_thunk o��< disable_irq �m�� __fentry__ � � � y i irq_madera GCC: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0 GCC: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0 �� � � � �� st Bc �� st Bc �� � � � � O � &� �r @ -� � @ 6� � � >� � � G� � �� < (8 s� @ T� t� � .c � hX � [� a h� @ w� � ` �D u� � |� �� �� �� �� �� �� �� �� �� �� �� �� �� � ,X �a � �a @ `T } � g w� � /� � �5 � @ ,� �x � :� �` @� 6 @ O� 6 H B� v� � \� } @ ,� c � "# � �X z� d� � p� � � ~� |� @ �� m � �� � �� �G � �� �G � �R 'm �� {� �l H }� y� �* �� �� � W � � � x� � x� � � "� � 6� � E� � arizona_ldo1_pdata arizona_micsupp_pdata madera_codec_pdata max_channels_clocked dmic_ref inmode out_mono pdm_fmt pdm_mute madera_pdata micvdd gpio_configs n_gpio_configs gpsw madera_type CS47L35 CS47L85 CS47L90 CS47L91 CS47L92 CS47L93 WM1840 CS47L15 CS42L92 MADERA_MCLK1 MADERA_MCLK2 MADERA_MCLK3 MADERA_NUM_MCLK madera regmap_32bit num_core_supplies core_supplies dcvdd internal_dcvdd reset_errata irq_dev num_micbias num_childbias dapm dapm_ptr_lock hp_ena out_clamp out_shorted snd_soc_dapm_context madera_irq_driver_exit madera_irq_driver_init madera_irq_probe madera_irq_remove madera_resume madera_resume_noirq madera_suspend madera_suspend_noirq irq-madera.ko �vB� v # � 2 @ ? � X � n � � � 8 � � � G � p 8 � P G � � 8 � � G � 8 * � G 8 8 8 P @ 6 b � � s 8 � @ � � p � " � � � � � ( @ ` + B 5 X D s b � � � � � � � � � � � � " ( 1 B U p � � __UNIQUE_ID_srcversion125 __UNIQUE_ID_depends124 ____versions __UNIQUE_ID_retpoline123 __UNIQUE_ID_intree122 __UNIQUE_ID_name121 __UNIQUE_ID_vermagic120 _note_9 _note_8 madera_resume_noirq __UNIQUE_ID_ddebug353.2 madera_suspend __UNIQUE_ID_ddebug351.4 madera_suspend_noirq __UNIQUE_ID_ddebug352.3 madera_resume __UNIQUE_ID_ddebug354.1 madera_irq_remove madera_irq_probe __UNIQUE_ID_ddebug355.0 madera_irq_chip madera_irq_probe.cold madera_irq_driver_init madera_irq_driver madera_irq_driver_exit __func__.12 __func__.11 __func__.10 __func__.9 __func__.8 __UNIQUE_ID_license359 __UNIQUE_ID_author358 __UNIQUE_ID_description357 __UNIQUE_ID_softdep356 madera_irq_pm_ops madera_irqs platform_driver_unregister __this_module cleanup_module enable_irq __dynamic_dev_dbg __fentry__ init_module regmap_add_irq_chip _dev_err irq_get_irq_data __x86_return_thunk __platform_driver_register regmap_update_bits_base regmap_del_irq_chip disable_irq 3 �������� < ��������' 8 ��������5 < p A 2 ��������Q 3 ��������k < ��������w 8 ��������� � � � 2 ��������� 3 ��������� 1 ��������� 8 ��������� � � � 2 ��������� 3 �������� 1 �������� 8 ��������% 6 , 8 1 2 ��������A 3 ��������j ; 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struct fwnode_handle; int gicv2m_init(struct fwnode_handle *parent_handle, struct irq_domain *parent); #endif /* __LINUX_IRQCHIP_ARM_GIC_COMMON_H */ PK Nt�Z�� � arm-gic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * include/linux/irqchip/arm-gic.h * * Copyright (C) 2002 ARM Limited, All Rights Reserved. */ #ifndef __LINUX_IRQCHIP_ARM_GIC_H #define __LINUX_IRQCHIP_ARM_GIC_H #define GIC_CPU_CTRL 0x00 #define GIC_CPU_PRIMASK 0x04 #define GIC_CPU_BINPOINT 0x08 #define GIC_CPU_INTACK 0x0c #define GIC_CPU_EOI 0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI 0x18 #define GIC_CPU_ALIAS_BINPOINT 0x1c #define GIC_CPU_ACTIVEPRIO 0xd0 #define GIC_CPU_IDENT 0xfc #define GIC_CPU_DEACTIVATE 0x1000 #define GICC_ENABLE 0x1 #define GICC_INT_PRI_THRESHOLD 0xf0 #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) #define GIC_CPU_CTRL_AckCtl_SHIFT 2 #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) #define GIC_CPU_CTRL_FIQEn_SHIFT 3 #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) #define GIC_CPU_CTRL_CBPR_SHIFT 4 #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) #define GICC_IAR_INT_ID_MASK 0x3ff #define GICC_INT_SPURIOUS 1023 #define GICC_DIS_BYPASS_MASK 0x1e0 #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 #define GIC_DIST_IIDR 0x008 #define GIC_DIST_IGROUP 0x080 #define GIC_DIST_ENABLE_SET 0x100 #define GIC_DIST_ENABLE_CLEAR 0x180 #define GIC_DIST_PENDING_SET 0x200 #define GIC_DIST_PENDING_CLEAR 0x280 #define GIC_DIST_ACTIVE_SET 0x300 #define GIC_DIST_ACTIVE_CLEAR 0x380 #define GIC_DIST_PRI 0x400 #define GIC_DIST_TARGET 0x800 #define GIC_DIST_CONFIG 0xc00 #define GIC_DIST_SOFTINT 0xf00 #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 #define GIC_DIST_SGI_PENDING_SET 0xf20 #define GICD_ENABLE 0x1 #define GICD_DISABLE 0x0 #define GICD_INT_ACTLOW_LVLTRIG 0x0 #define GICD_INT_EN_CLR_X32 0xffffffff #define GICD_INT_EN_SET_SGI 0x0000ffff #define GICD_INT_EN_CLR_PPI 0xffff0000 #define GICD_IIDR_IMPLEMENTER_SHIFT 0 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) #define GICD_IIDR_REVISION_SHIFT 12 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) #define GICD_IIDR_VARIANT_SHIFT 16 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) #define GICD_IIDR_PRODUCT_ID_SHIFT 24 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) #define GICH_HCR 0x0 #define GICH_VTR 0x4 #define GICH_VMCR 0x8 #define GICH_MISR 0x10 #define GICH_EISR0 0x20 #define GICH_EISR1 0x24 #define GICH_ELRSR0 0x30 #define GICH_ELRSR1 0x34 #define GICH_APR 0xf0 #define GICH_LR0 0x100 #define GICH_HCR_EN (1 << 0) #define GICH_HCR_UIE (1 << 1) #define GICH_HCR_NPIE (1 << 3) #define GICH_LR_VIRTUALID (0x3ff << 0) #define GICH_LR_PHYSID_CPUID_SHIFT (10) #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) #define GICH_LR_PRIORITY_SHIFT 23 #define GICH_LR_STATE (3 << 28) #define GICH_LR_PENDING_BIT (1 << 28) #define GICH_LR_ACTIVE_BIT (1 << 29) #define GICH_LR_EOI (1 << 19) #define GICH_LR_GROUP1 (1 << 30) #define GICH_LR_HW (1 << 31) #define GICH_VMCR_ENABLE_GRP0_SHIFT 0 #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) #define GICH_VMCR_ENABLE_GRP1_SHIFT 1 #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) #define GICH_VMCR_ACK_CTL_SHIFT 2 #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) #define GICH_VMCR_FIQ_EN_SHIFT 3 #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) #define GICH_VMCR_CBPR_SHIFT 4 #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) #define GICH_VMCR_EOI_MODE_SHIFT 9 #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) #define GICH_VMCR_PRIMASK_SHIFT 27 #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) #define GICH_VMCR_BINPOINT_SHIFT 21 #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) #define GICH_MISR_EOI (1 << 0) #define GICH_MISR_U (1 << 1) #define GICV_PMR_PRIORITY_SHIFT 3 #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) #ifndef __ASSEMBLY__ #include <linux/irqdomain.h> struct device_node; struct gic_chip_data; void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); int gic_cpu_if_down(unsigned int gic_nr); void gic_cpu_save(struct gic_chip_data *gic); void gic_cpu_restore(struct gic_chip_data *gic); void gic_dist_save(struct gic_chip_data *gic); void gic_dist_restore(struct gic_chip_data *gic); /* * Subdrivers that need some preparatory work can initialize their * chips and call this to register their GICs. */ int gic_of_init(struct device_node *node, struct device_node *parent); /* * Initialises and registers a non-root or child GIC chip. Memory for * the gic_chip_data structure is dynamically allocated. */ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); /* * Legacy platforms not converted to DT yet must use this to init * their GIC */ void gic_init(void __iomem *dist , void __iomem *cpu); void gic_send_sgi(unsigned int cpu_id, unsigned int irq); int gic_get_cpu_id(unsigned int cpu); void gic_migrate_target(unsigned int new_cpu_id); unsigned long gic_get_sgir_physaddr(void); #endif /* __ASSEMBLY */ #endif PK Nt�Z I�� � irq-bcm2836.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Root interrupt controller for the BCM2836 (Raspberry Pi 2). * * Copyright 2015 Broadcom */ #define LOCAL_CONTROL 0x000 #define LOCAL_PRESCALER 0x008 /* * The low 2 bits identify the CPU that the GPU IRQ goes to, and the * next 2 bits identify the CPU that the GPU FIQ goes to. */ #define LOCAL_GPU_ROUTING 0x00c /* When setting bits 0-3, enables PMU interrupts on that CPU. */ #define LOCAL_PM_ROUTING_SET 0x010 /* When setting bits 0-3, disables PMU interrupts on that CPU. */ #define LOCAL_PM_ROUTING_CLR 0x014 /* * The low 4 bits of this are the CPU's timer IRQ enables, and the * next 4 bits are the CPU's timer FIQ enables (which override the IRQ * bits). */ #define LOCAL_TIMER_INT_CONTROL0 0x040 /* * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and * the next 4 bits are the CPU's per-mailbox FIQ enables (which * override the IRQ bits). */ #define LOCAL_MAILBOX_INT_CONTROL0 0x050 /* * The CPU's interrupt status register. Bits are defined by the * LOCAL_IRQ_* bits below. */ #define LOCAL_IRQ_PENDING0 0x060 /* Same status bits as above, but for FIQ. */ #define LOCAL_FIQ_PENDING0 0x070 /* * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and * these bits are organized by mailbox number and then CPU number. We * use mailbox 0 for IPIs. The mailbox's interrupt is raised while * any bit is set. */ #define LOCAL_MAILBOX0_SET0 0x080 #define LOCAL_MAILBOX3_SET0 0x08c /* Mailbox write-to-clear bits. */ #define LOCAL_MAILBOX0_CLR0 0x0c0 #define LOCAL_MAILBOX3_CLR0 0x0cc #define LOCAL_IRQ_CNTPSIRQ 0 #define LOCAL_IRQ_CNTPNSIRQ 1 #define LOCAL_IRQ_CNTHPIRQ 2 #define LOCAL_IRQ_CNTVIRQ 3 #define LOCAL_IRQ_MAILBOX0 4 #define LOCAL_IRQ_MAILBOX1 5 #define LOCAL_IRQ_MAILBOX2 6 #define LOCAL_IRQ_MAILBOX3 7 #define LOCAL_IRQ_GPU_FAST 8 #define LOCAL_IRQ_PMU_FAST 9 #define LAST_IRQ LOCAL_IRQ_PMU_FAST PK Nt�ZJk�̛ � mmp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __IRQCHIP_MMP_H #define __IRQCHIP_MMP_H extern struct irq_chip icu_irq_chip; #endif /* __IRQCHIP_MMP_H */ PK Nt�Zۜ��d d irq-sa11x0.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Generic IRQ handling for the SA11x0. * * Copyright (C) 2015 Dmitry Eremin-Solenikov * Copyright (C) 1999-2001 Nicolas Pitre */ #ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_SA11x0_H #define __INCLUDE_LINUX_IRQCHIP_IRQ_SA11x0_H void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start); #endif PK Nt�ZҸ� irq-ixp4xx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __IRQ_IXP4XX_H #define __IRQ_IXP4XX_H #include <linux/ioport.h> struct irq_domain; void ixp4xx_irq_init(resource_size_t irqbase, bool is_356); struct irq_domain *ixp4xx_get_irq_domain(void); #endif /* __IRQ_IXP4XX_H */ PK Nt�Z����7 7 irq-omap-intc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /** * irq-omap-intc.h - INTC Idle Functions * * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com * * Author: Felipe Balbi <balbi@ti.com> */ #ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_OMAP_INTC_H #define __INCLUDE_LINUX_IRQCHIP_IRQ_OMAP_INTC_H int omap_irq_pending(void); void omap_intc_save_context(void); void omap_intc_restore_context(void); void omap3_intc_suspend(void); void omap3_intc_prepare_idle(void); void omap3_intc_resume_idle(void); #endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_OMAP_INTC_H */ PK Nt�Z�`��a a versatile-fpga.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef PLAT_FPGA_IRQ_H #define PLAT_FPGA_IRQ_H struct device_node; struct pt_regs; void fpga_handle_irq(struct pt_regs *regs); void fpga_irq_init(void __iomem *, const char *, int, int, u32, struct device_node *node); int fpga_irq_of_init(struct device_node *node, struct device_node *parent); #endif PK Nt�Z����� � arm-vgic-info.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * include/linux/irqchip/arm-vgic-info.h * * Copyright (C) 2016 ARM Limited, All Rights Reserved. */ #ifndef __LINUX_IRQCHIP_ARM_VGIC_INFO_H #define __LINUX_IRQCHIP_ARM_VGIC_INFO_H #include <linux/types.h> #include <linux/ioport.h> enum gic_type { /* Full GICv2 */ GIC_V2, /* Full GICv3, optionally with v2 compat */ GIC_V3, }; struct gic_kvm_info { /* GIC type */ enum gic_type type; /* Virtual CPU interface */ struct resource vcpu; /* Interrupt number */ unsigned int maint_irq; /* No interrupt mask, no need to use the above field */ bool no_maint_irq_mask; /* Virtual control interface */ struct resource vctrl; /* vlpi support */ bool has_v4; /* rvpeid support */ bool has_v4_1; /* Deactivation impared, subpar stuff */ bool no_hw_deactivation; }; #ifdef CONFIG_KVM void vgic_set_kvm_info(const struct gic_kvm_info *info); #else static inline void vgic_set_kvm_info(const struct gic_kvm_info *info) {} #endif #endif PK Nt�Z�L� _ _ arm-gic-v3.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. * Author: Marc Zyngier <marc.zyngier@arm.com> */ #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H #define __LINUX_IRQCHIP_ARM_GIC_V3_H /* * Distributor registers. We assume we're running non-secure, with ARE * being set. Secure-only and non-ARE registers are not described. */ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 #define GICD_IIDR 0x0008 #define GICD_TYPER2 0x000C #define GICD_STATUSR 0x0010 #define GICD_SETSPI_NSR 0x0040 #define GICD_CLRSPI_NSR 0x0048 #define GICD_SETSPI_SR 0x0050 #define GICD_CLRSPI_SR 0x0058 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_ICENABLER 0x0180 #define GICD_ISPENDR 0x0200 #define GICD_ICPENDR 0x0280 #define GICD_ISACTIVER 0x0300 #define GICD_ICACTIVER 0x0380 #define GICD_IPRIORITYR 0x0400 #define GICD_ICFGR 0x0C00 #define GICD_IGRPMODR 0x0D00 #define GICD_NSACR 0x0E00 #define GICD_IGROUPRnE 0x1000 #define GICD_ISENABLERnE 0x1200 #define GICD_ICENABLERnE 0x1400 #define GICD_ISPENDRnE 0x1600 #define GICD_ICPENDRnE 0x1800 #define GICD_ISACTIVERnE 0x1A00 #define GICD_ICACTIVERnE 0x1C00 #define GICD_IPRIORITYRnE 0x2000 #define GICD_ICFGRnE 0x3000 #define GICD_IROUTER 0x6000 #define GICD_IROUTERnE 0x8000 #define GICD_IDREGS 0xFFD0 #define GICD_PIDR2 0xFFE8 #define ESPI_BASE_INTID 4096 /* * Those registers are actually from GICv2, but the spec demands that they * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). */ #define GICD_ITARGETSR 0x0800 #define GICD_SGIR 0x0F00 #define GICD_CPENDSGIR 0x0F10 #define GICD_SPENDSGIR 0x0F20 #define GICD_CTLR_RWP (1U << 31) #define GICD_CTLR_nASSGIreq (1U << 8) #define GICD_CTLR_DS (1U << 6) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) #define GICD_IIDR_IMPLEMENTER_SHIFT 0 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) #define GICD_IIDR_REVISION_SHIFT 12 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) #define GICD_IIDR_VARIANT_SHIFT 16 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) #define GICD_IIDR_PRODUCT_ID_SHIFT 24 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) /* * In systems with a single security state (what we emulate in KVM) * the meaning of the interrupt group enable bits is slightly different */ #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) #define GICD_TYPER_RSS (1U << 26) #define GICD_TYPER_LPIS (1U << 17) #define GICD_TYPER_MBIS (1U << 16) #define GICD_TYPER_ESPI (1U << 8) #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) #define GICD_TYPER_ESPIS(typer) \ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) #define GICD_TYPER2_nASSGIcap (1U << 8) #define GICD_TYPER2_VIL (1U << 7) #define GICD_TYPER2_VID GENMASK(4, 0) #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) #define GIC_PIDR2_ARCH_MASK 0xf0 #define GIC_PIDR2_ARCH_GICv3 0x30 #define GIC_PIDR2_ARCH_GICv4 0x40 #define GIC_V3_DIST_SIZE 0x10000 #define GIC_PAGE_SIZE_4K 0ULL #define GIC_PAGE_SIZE_16K 1ULL #define GIC_PAGE_SIZE_64K 2ULL #define GIC_PAGE_SIZE_MASK 3ULL /* * Re-Distributor registers, offsets from RD_base */ #define GICR_CTLR GICD_CTLR #define GICR_IIDR 0x0004 #define GICR_TYPER 0x0008 #define GICR_STATUSR GICD_STATUSR #define GICR_WAKER 0x0014 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_PROPBASER 0x0070 #define GICR_PENDBASER 0x0078 #define GICR_INVLPIR 0x00A0 #define GICR_INVALLR 0x00B0 #define GICR_SYNCR 0x00C0 #define GICR_IDREGS GICD_IDREGS #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) #define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) #define EPPI_BASE_INTID 1056 #define GICR_TYPER_NR_PPIS(r) \ ({ \ unsigned int __ppinum = ((r) >> 27) & 0x1f; \ unsigned int __nr_ppis = 16; \ if (__ppinum == 1 || __ppinum == 2) \ __nr_ppis += __ppinum * 32; \ \ __nr_ppis; \ }) #define GICR_WAKER_ProcessorSleep (1U << 1) #define GICR_WAKER_ChildrenAsleep (1U << 2) #define GIC_BASER_CACHE_nCnB 0ULL #define GIC_BASER_CACHE_SameAsInner 0ULL #define GIC_BASER_CACHE_nC 1ULL #define GIC_BASER_CACHE_RaWt 2ULL #define GIC_BASER_CACHE_RaWb 3ULL #define GIC_BASER_CACHE_WaWt 4ULL #define GIC_BASER_CACHE_WaWb 5ULL #define GIC_BASER_CACHE_RaWaWt 6ULL #define GIC_BASER_CACHE_RaWaWb 7ULL #define GIC_BASER_CACHE_MASK 7ULL #define GIC_BASER_NonShareable 0ULL #define GIC_BASER_InnerShareable 1ULL #define GIC_BASER_OuterShareable 2ULL #define GIC_BASER_SHAREABILITY_MASK 3ULL #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) #define GIC_BASER_SHAREABILITY(reg, type) \ (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) /* encode a size field of width @w containing @n - 1 units */ #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) #define GICR_PROPBASER_SHAREABILITY_SHIFT (10) #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) #define GICR_PROPBASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK #define GICR_PROPBASER_InnerShareable \ GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB) #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC) #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt) #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb) #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt) #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb) #define GICR_PROPBASER_IDBITS_MASK (0x1f) #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) #define GICR_PENDBASER_SHAREABILITY_SHIFT (10) #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) #define GICR_PENDBASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK #define GICR_PENDBASER_InnerShareable \ GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB) #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC) #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt) #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb) #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt) #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb) #define GICR_PENDBASER_PTZ BIT_ULL(62) /* * Re-Distributor registers, offsets from SGI_base */ #define GICR_IGROUPR0 GICD_IGROUPR #define GICR_ISENABLER0 GICD_ISENABLER #define GICR_ICENABLER0 GICD_ICENABLER #define GICR_ISPENDR0 GICD_ISPENDR #define GICR_ICPENDR0 GICD_ICPENDR #define GICR_ISACTIVER0 GICD_ISACTIVER #define GICR_ICACTIVER0 GICD_ICACTIVER #define GICR_IPRIORITYR0 GICD_IPRIORITYR #define GICR_ICFGR0 GICD_ICFGR #define GICR_IGRPMODR0 GICD_IGRPMODR #define GICR_NSACR GICD_NSACR #define GICR_TYPER_PLPIS (1U << 0) #define GICR_TYPER_VLPIS (1U << 1) #define GICR_TYPER_DIRTY (1U << 2) #define GICR_TYPER_DirectLPIS (1U << 3) #define GICR_TYPER_LAST (1U << 4) #define GICR_TYPER_RVPEID (1U << 7) #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0) #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) #define GICR_INVLPIR_V GENMASK_ULL(63, 63) #define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID #define GICR_INVALLR_V GICR_INVLPIR_V #define GIC_V3_REDIST_SIZE 0x20000 #define LPI_PROP_GROUP1 (1 << 1) #define LPI_PROP_ENABLED (1 << 0) /* * Re-Distributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER 0x0070 #define GICR_VPROPBASER_IDBITS_MASK 0x1f #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10) #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7) #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56) #define GICR_VPROPBASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK) #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK) #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK) #define GICR_VPROPBASER_CACHEABILITY_MASK \ GICR_VPROPBASER_INNER_CACHEABILITY_MASK #define GICR_VPROPBASER_InnerShareable \ GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable) #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB) #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC) #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt) #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb) #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt) #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb) #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt) #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb) /* * GICv4.1 VPROPBASER reinvention. A subtle mix between the old * VPROPBASER and ITS_BASER. Just not quite any of the two. */ #define GICR_VPROPBASER_4_1_VALID (1ULL << 63) #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59) #define GICR_VPROPBASER_4_1_INDIRECT (1ULL << 55) #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53) #define GICR_VPROPBASER_4_1_Z (1ULL << 52) #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12) #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0) #define GICR_VPENDBASER 0x0078 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10) #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7) #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56) #define GICR_VPENDBASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK) #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK) #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK) #define GICR_VPENDBASER_CACHEABILITY_MASK \ GICR_VPENDBASER_INNER_CACHEABILITY_MASK #define GICR_VPENDBASER_NonShareable \ GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable) #define GICR_VPENDBASER_InnerShareable \ GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable) #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB) #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC) #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt) #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb) #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt) #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb) #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt) #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb) #define GICR_VPENDBASER_Dirty (1ULL << 60) #define GICR_VPENDBASER_PendingLast (1ULL << 61) #define GICR_VPENDBASER_IDAI (1ULL << 62) #define GICR_VPENDBASER_Valid (1ULL << 63) /* * GICv4.1 VPENDBASER, used for VPE residency. On top of these fields, * also use the above Valid, PendingLast and Dirty. */ #define GICR_VPENDBASER_4_1_DB (1ULL << 62) #define GICR_VPENDBASER_4_1_VGRP0EN (1ULL << 59) #define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58) #define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0) #define GICR_VSGIR 0x0080 #define GICR_VSGIR_VPEID GENMASK(15, 0) #define GICR_VSGIPENDR 0x0088 #define GICR_VSGIPENDR_BUSY (1U << 31) #define GICR_VSGIPENDR_PENDING GENMASK(15, 0) /* * ITS registers, offsets from ITS_base */ #define GITS_CTLR 0x0000 #define GITS_IIDR 0x0004 #define GITS_TYPER 0x0008 #define GITS_MPIDR 0x0018 #define GITS_CBASER 0x0080 #define GITS_CWRITER 0x0088 #define GITS_CREADR 0x0090 #define GITS_BASER 0x0100 #define GITS_IDREGS_BASE 0xffd0 #define GITS_PIDR0 0xffe0 #define GITS_PIDR1 0xffe4 #define GITS_PIDR2 GICR_PIDR2 #define GITS_PIDR4 0xffd0 #define GITS_CIDR0 0xfff0 #define GITS_CIDR1 0xfff4 #define GITS_CIDR2 0xfff8 #define GITS_CIDR3 0xfffc #define GITS_TRANSLATER 0x10040 #define GITS_SGIR 0x20020 #define GITS_SGIR_VPEID GENMASK_ULL(47, 32) #define GITS_SGIR_VINTID GENMASK_ULL(3, 0) #define GITS_CTLR_ENABLE (1U << 0) #define GITS_CTLR_ImDe (1U << 1) #define GITS_CTLR_ITS_NUMBER_SHIFT 4 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) #define GITS_CTLR_QUIESCENT (1U << 31) #define GITS_TYPER_PLPIS (1UL << 0) #define GITS_TYPER_VLPIS (1UL << 1) #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) #define GITS_TYPER_IDBITS_SHIFT 8 #define GITS_TYPER_DEVBITS_SHIFT 13 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13) #define GITS_TYPER_PTA (1UL << 19) #define GITS_TYPER_HCC_SHIFT 24 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) #define GITS_TYPER_VMOVP (1ULL << 37) #define GITS_TYPER_VMAPP (1ULL << 40) #define GITS_TYPER_SVPET GENMASK_ULL(42, 41) #define GITS_IIDR_REV_SHIFT 12 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT) #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf) #define GITS_IIDR_PRODUCTID_SHIFT 24 #define GITS_CBASER_VALID (1ULL << 63) #define GITS_CBASER_SHAREABILITY_SHIFT (10) #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) #define GITS_CBASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) #define GITS_CBASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) #define GITS_CBASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK #define GITS_CBASER_InnerShareable \ GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb) #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12)) #define GITS_BASER_NR_REGS 8 #define GITS_BASER_VALID (1ULL << 63) #define GITS_BASER_INDIRECT (1ULL << 62) #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) #define GITS_BASER_INNER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK #define GITS_BASER_OUTER_CACHEABILITY_MASK \ GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) #define GITS_BASER_SHAREABILITY_MASK \ GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK) #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC) #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt) #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb) #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt) #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb) #define GITS_BASER_TYPE_SHIFT (56) #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) #define GITS_BASER_ENTRY_SIZE_SHIFT (48) #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) #define GITS_BASER_PHYS_52_to_48(phys) \ (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) #define GITS_BASER_ADDR_48_to_52(baser) \ (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) #define GITS_BASER_SHAREABILITY_SHIFT (10) #define GITS_BASER_InnerShareable \ GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) #define GITS_BASER_PAGE_SIZE_SHIFT (8) #define __GITS_BASER_PSZ(sz) (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT) #define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K) #define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K) #define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K) #define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK) #define GITS_BASER_PAGES_MAX 256 #define GITS_BASER_PAGES_SHIFT (0) #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) #define GITS_BASER_TYPE_NONE 0 #define GITS_BASER_TYPE_DEVICE 1 #define GITS_BASER_TYPE_VCPU 2 #define GITS_BASER_TYPE_RESERVED3 3 #define GITS_BASER_TYPE_COLLECTION 4 #define GITS_BASER_TYPE_RESERVED5 5 #define GITS_BASER_TYPE_RESERVED6 6 #define GITS_BASER_TYPE_RESERVED7 7 #define GITS_LVL1_ENTRY_SIZE (8UL) /* * ITS commands */ #define GITS_CMD_MAPD 0x08 #define GITS_CMD_MAPC 0x09 #define GITS_CMD_MAPTI 0x0a #define GITS_CMD_MAPI 0x0b #define GITS_CMD_MOVI 0x01 #define GITS_CMD_DISCARD 0x0f #define GITS_CMD_INV 0x0c #define GITS_CMD_MOVALL 0x0e #define GITS_CMD_INVALL 0x0d #define GITS_CMD_INT 0x03 #define GITS_CMD_CLEAR 0x04 #define GITS_CMD_SYNC 0x05 /* * GICv4 ITS specific commands */ #define GITS_CMD_GICv4(x) ((x) | 0x20) #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL) #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC) #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI) #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI) #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC) /* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */ #define GITS_CMD_VMOVP GITS_CMD_GICv4(2) #define GITS_CMD_VSGI GITS_CMD_GICv4(3) #define GITS_CMD_INVDB GITS_CMD_GICv4(0xe) /* * ITS error numbers */ #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 #define E_ITS_MAPD_DEVICE_OOR 0x010801 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802 #define E_ITS_MAPC_PROCNUM_OOR 0x010902 #define E_ITS_MAPC_COLLECTION_OOR 0x010903 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 #define E_ITS_MAPTI_ID_OOR 0x010a05 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 /* * CPU interface registers */ #define ICC_CTLR_EL1_EOImode_SHIFT (1) #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT) #define ICC_CTLR_EL1_CBPR_SHIFT 0 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) #define ICC_CTLR_EL1_PMHE_SHIFT 6 #define ICC_CTLR_EL1_PMHE_MASK (1 << ICC_CTLR_EL1_PMHE_SHIFT) #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) #define ICC_CTLR_EL1_ID_BITS_SHIFT 11 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT) #define ICC_CTLR_EL1_SEIS_SHIFT 14 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT) #define ICC_CTLR_EL1_A3V_SHIFT 15 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) #define ICC_CTLR_EL1_RSS (0x1 << 18) #define ICC_CTLR_EL1_ExtRange (0x1 << 19) #define ICC_PMR_EL1_SHIFT 0 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) #define ICC_BPR0_EL1_SHIFT 0 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT) #define ICC_BPR1_EL1_SHIFT 0 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT) #define ICC_IGRPEN0_EL1_SHIFT 0 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT) #define ICC_IGRPEN1_EL1_SHIFT 0 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT) #define ICC_SRE_EL1_DIB (1U << 2) #define ICC_SRE_EL1_DFB (1U << 1) #define ICC_SRE_EL1_SRE (1U << 0) /* These are for GICv2 emulation only */ #define GICH_LR_VIRTUALID (0x3ffUL << 0) #define GICH_LR_PHYSID_CPUID_SHIFT (10) #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) #define ICC_IAR1_EL1_SPURIOUS 0x3ff #define ICC_SRE_EL2_SRE (1 << 0) #define ICC_SRE_EL2_ENABLE (1 << 3) #define ICC_SGI1R_TARGET_LIST_SHIFT 0 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) #define ICC_SGI1R_AFFINITY_1_SHIFT 16 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) #define ICC_SGI1R_SGI_ID_SHIFT 24 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) #define ICC_SGI1R_AFFINITY_2_SHIFT 32 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 #define ICC_SGI1R_RS_SHIFT 44 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT) #define ICC_SGI1R_AFFINITY_3_SHIFT 48 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) #include <asm/arch_gicv3.h> #ifndef __ASSEMBLY__ /* * We need a value to serve as a irq-type for LPIs. Choose one that will * hopefully pique the interest of the reviewer. */ #define GIC_IRQ_TYPE_LPI 0xa110c8ed struct rdists { struct { raw_spinlock_t rd_lock; void __iomem *rd_base; struct page *pend_page; phys_addr_t phys_base; bool lpi_enabled; cpumask_t *vpe_table_mask; void *vpe_l1_base; } __percpu *rdist; phys_addr_t prop_table_pa; void *prop_table_va; u64 flags; u32 gicd_typer; u32 gicd_typer2; bool has_vlpis; bool has_rvpeid; bool has_direct_lpi; bool has_vpend_valid_dirty; }; struct irq_domain; struct fwnode_handle; int its_cpu_init(void); int its_init(struct fwnode_handle *handle, struct rdists *rdists, struct irq_domain *domain); int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent); static inline bool gic_enable_sre(void) { u32 val; val = gic_read_sre(); if (val & ICC_SRE_EL1_SRE) return true; val |= ICC_SRE_EL1_SRE; gic_write_sre(val); val = gic_read_sre(); return !!(val & ICC_SRE_EL1_SRE); } #endif #endif PK Nt�Z�x2h h irq-davinci-cp-intc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2019 Texas Instruments */ #ifndef _LINUX_IRQ_DAVINCI_CP_INTC_ #define _LINUX_IRQ_DAVINCI_CP_INTC_ #include <linux/ioport.h> /** * struct davinci_cp_intc_config - configuration data for davinci-cp-intc * driver. * * @reg: register range to map * @num_irqs: number of HW interrupts supported by the controller */ struct davinci_cp_intc_config { struct resource reg; unsigned int num_irqs; }; int davinci_cp_intc_init(const struct davinci_cp_intc_config *config); #endif /* _LINUX_IRQ_DAVINCI_CP_INTC_ */ PK Nt�Z�' xtensa-pic.hnu �[��� /* * Xtensa built-in interrupt controller * * Copyright (C) 2002 - 2013 Tensilica, Inc. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef __LINUX_IRQCHIP_XTENSA_PIC_H #define __LINUX_IRQCHIP_XTENSA_PIC_H struct device_node; int xtensa_pic_init_legacy(struct device_node *interrupt_parent); #endif /* __LINUX_IRQCHIP_XTENSA_PIC_H */ PK Nt�Z���>� � chained_irq.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Chained IRQ handlers support. * * Copyright (C) 2011 ARM Ltd. */ #ifndef __IRQCHIP_CHAINED_IRQ_H #define __IRQCHIP_CHAINED_IRQ_H #include <linux/irq.h> /* * Entry/exit functions for chained handlers where the primary IRQ chip * may implement either fasteoi or level-trigger flow control. */ static inline void chained_irq_enter(struct irq_chip *chip, struct irq_desc *desc) { /* FastEOI controllers require no action on entry. */ if (chip->irq_eoi) return; if (chip->irq_mask_ack) { chip->irq_mask_ack(&desc->irq_data); } else { chip->irq_mask(&desc->irq_data); if (chip->irq_ack) chip->irq_ack(&desc->irq_data); } } static inline void chained_irq_exit(struct irq_chip *chip, struct irq_desc *desc) { if (chip->irq_eoi) chip->irq_eoi(&desc->irq_data); else chip->irq_unmask(&desc->irq_data); } #endif /* __IRQCHIP_CHAINED_IRQ_H */ PK Nt�ZACR6 6 arm-gic-v4.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016,2017 ARM Limited, All Rights Reserved. * Author: Marc Zyngier <marc.zyngier@arm.com> */ #ifndef __LINUX_IRQCHIP_ARM_GIC_V4_H #define __LINUX_IRQCHIP_ARM_GIC_V4_H struct its_vpe; /* * Maximum number of ITTs when GITS_TYPER.VMOVP == 0, using the * ITSList mechanism to perform inter-ITS synchronization. */ #define GICv4_ITS_LIST_MAX 16 /* Embedded in kvm.arch */ struct its_vm { struct fwnode_handle *fwnode; struct irq_domain *domain; struct page *vprop_page; struct its_vpe **vpes; int nr_vpes; irq_hw_number_t db_lpi_base; unsigned long *db_bitmap; int nr_db_lpis; u32 vlpi_count[GICv4_ITS_LIST_MAX]; }; /* Embedded in kvm_vcpu.arch */ struct its_vpe { struct page *vpt_page; struct its_vm *its_vm; /* per-vPE VLPI tracking */ atomic_t vlpi_count; /* Doorbell interrupt */ int irq; irq_hw_number_t vpe_db_lpi; /* VPE resident */ bool resident; /* VPT parse complete */ bool ready; union { /* GICv4.0 implementations */ struct { /* VPE proxy mapping */ int vpe_proxy_event; /* Implementation Defined Area Invalid */ bool idai; }; /* GICv4.1 implementations */ struct { struct fwnode_handle *fwnode; struct irq_domain *sgi_domain; struct { u8 priority; bool enabled; bool group; } sgi_config[16]; }; }; /* Track the VPE being mapped */ atomic_t vmapp_count; /* * Ensures mutual exclusion between affinity setting of the * vPE and vLPI operations using vpe->col_idx. */ raw_spinlock_t vpe_lock; /* * This collection ID is used to indirect the target * redistributor for this VPE. The ID itself isn't involved in * programming of the ITS. */ u16 col_idx; /* Unique (system-wide) VPE identifier */ u16 vpe_id; /* Pending VLPIs on schedule out? */ bool pending_last; }; /* * struct its_vlpi_map: structure describing the mapping of a * VLPI. Only to be interpreted in the context of a physical interrupt * it complements. To be used as the vcpu_info passed to * irq_set_vcpu_affinity(). * * @vm: Pointer to the GICv4 notion of a VM * @vpe: Pointer to the GICv4 notion of a virtual CPU (VPE) * @vintid: Virtual LPI number * @properties: Priority and enable bits (as written in the prop table) * @db_enabled: Is the VPE doorbell to be generated? */ struct its_vlpi_map { struct its_vm *vm; struct its_vpe *vpe; u32 vintid; u8 properties; bool db_enabled; }; enum its_vcpu_info_cmd_type { MAP_VLPI, GET_VLPI, PROP_UPDATE_VLPI, PROP_UPDATE_AND_INV_VLPI, SCHEDULE_VPE, DESCHEDULE_VPE, COMMIT_VPE, INVALL_VPE, PROP_UPDATE_VSGI, }; struct its_cmd_info { enum its_vcpu_info_cmd_type cmd_type; union { struct its_vlpi_map *map; u8 config; bool req_db; struct { bool g0en; bool g1en; }; struct { u8 priority; bool group; }; }; }; int its_alloc_vcpu_irqs(struct its_vm *vm); void its_free_vcpu_irqs(struct its_vm *vm); int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en); int its_make_vpe_non_resident(struct its_vpe *vpe, bool db); int its_commit_vpe(struct its_vpe *vpe); int its_invall_vpe(struct its_vpe *vpe); int its_map_vlpi(int irq, struct its_vlpi_map *map); int its_get_vlpi(int irq, struct its_vlpi_map *map); int its_unmap_vlpi(int irq); int its_prop_update_vlpi(int irq, u8 config, bool inv); int its_prop_update_vsgi(int irq, u8 priority, bool group); struct irq_domain_ops; int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *vpe_ops, const struct irq_domain_ops *sgi_ops); bool gic_cpuif_has_vsgi(void); #endif PK Nt�Z�"D�K K irq-partition-percpu.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2016 ARM Limited, All Rights Reserved. * Author: Marc Zyngier <marc.zyngier@arm.com> */ #ifndef __LINUX_IRQCHIP_IRQ_PARTITION_PERCPU_H #define __LINUX_IRQCHIP_IRQ_PARTITION_PERCPU_H #include <linux/fwnode.h> #include <linux/cpumask.h> #include <linux/irqdomain.h> struct partition_affinity { cpumask_t mask; void *partition_id; }; struct partition_desc; #ifdef CONFIG_PARTITION_PERCPU int partition_translate_id(struct partition_desc *desc, void *partition_id); struct partition_desc *partition_create_desc(struct fwnode_handle *fwnode, struct partition_affinity *parts, int nr_parts, int chained_irq, const struct irq_domain_ops *ops); struct irq_domain *partition_get_domain(struct partition_desc *dsc); #else static inline int partition_translate_id(struct partition_desc *desc, void *partition_id) { return -EINVAL; } static inline struct partition_desc *partition_create_desc(struct fwnode_handle *fwnode, struct partition_affinity *parts, int nr_parts, int chained_irq, const struct irq_domain_ops *ops) { return NULL; } static inline struct irq_domain *partition_get_domain(struct partition_desc *dsc) { return NULL; } #endif #endif /* __LINUX_IRQCHIP_IRQ_PARTITION_PERCPU_H */ PK Nt�Z�2ba a arm-vic.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * arch/arm/include/asm/hardware/vic.h * * Copyright (c) ARM Limited 2003. All rights reserved. */ #ifndef __ASM_ARM_HARDWARE_VIC_H #define __ASM_ARM_HARDWARE_VIC_H #include <linux/types.h> void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); #endif PK Nt�Z�f6� � mxs.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. */ #ifndef __LINUX_IRQCHIP_MXS_H #define __LINUX_IRQCHIP_MXS_H extern void icoll_handle_irq(struct pt_regs *); #endif PK Nt�Z�*� � xtensa-mx.hnu �[��� /* * Xtensa MX interrupt distributor * * Copyright (C) 2002 - 2013 Tensilica, Inc. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef __LINUX_IRQCHIP_XTENSA_MX_H #define __LINUX_IRQCHIP_XTENSA_MX_H struct device_node; int xtensa_mx_init_legacy(struct device_node *interrupt_parent); #endif /* __LINUX_IRQCHIP_XTENSA_MX_H */ PK Nt�Z���ա � irq-madera.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Interrupt support for Cirrus Logic Madera codecs * * Copyright (C) 2016-2018 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. */ #ifndef IRQCHIP_MADERA_H #define IRQCHIP_MADERA_H #include <linux/interrupt.h> #include <linux/mfd/madera/core.h> #define MADERA_IRQ_FLL1_LOCK 0 #define MADERA_IRQ_FLL2_LOCK 1 #define MADERA_IRQ_FLL3_LOCK 2 #define MADERA_IRQ_FLLAO_LOCK 3 #define MADERA_IRQ_CLK_SYS_ERR 4 #define MADERA_IRQ_CLK_ASYNC_ERR 5 #define MADERA_IRQ_CLK_DSP_ERR 6 #define MADERA_IRQ_HPDET 7 #define MADERA_IRQ_MICDET1 8 #define MADERA_IRQ_MICDET2 9 #define MADERA_IRQ_JD1_RISE 10 #define MADERA_IRQ_JD1_FALL 11 #define MADERA_IRQ_JD2_RISE 12 #define MADERA_IRQ_JD2_FALL 13 #define MADERA_IRQ_MICD_CLAMP_RISE 14 #define MADERA_IRQ_MICD_CLAMP_FALL 15 #define MADERA_IRQ_DRC2_SIG_DET 16 #define MADERA_IRQ_DRC1_SIG_DET 17 #define MADERA_IRQ_ASRC1_IN1_LOCK 18 #define MADERA_IRQ_ASRC1_IN2_LOCK 19 #define MADERA_IRQ_ASRC2_IN1_LOCK 20 #define MADERA_IRQ_ASRC2_IN2_LOCK 21 #define MADERA_IRQ_DSP_IRQ1 22 #define MADERA_IRQ_DSP_IRQ2 23 #define MADERA_IRQ_DSP_IRQ3 24 #define MADERA_IRQ_DSP_IRQ4 25 #define MADERA_IRQ_DSP_IRQ5 26 #define MADERA_IRQ_DSP_IRQ6 27 #define MADERA_IRQ_DSP_IRQ7 28 #define MADERA_IRQ_DSP_IRQ8 29 #define MADERA_IRQ_DSP_IRQ9 30 #define MADERA_IRQ_DSP_IRQ10 31 #define MADERA_IRQ_DSP_IRQ11 32 #define MADERA_IRQ_DSP_IRQ12 33 #define MADERA_IRQ_DSP_IRQ13 34 #define MADERA_IRQ_DSP_IRQ14 35 #define MADERA_IRQ_DSP_IRQ15 36 #define MADERA_IRQ_DSP_IRQ16 37 #define MADERA_IRQ_HP1L_SC 38 #define MADERA_IRQ_HP1R_SC 39 #define MADERA_IRQ_HP2L_SC 40 #define MADERA_IRQ_HP2R_SC 41 #define MADERA_IRQ_HP3L_SC 42 #define MADERA_IRQ_HP3R_SC 43 #define MADERA_IRQ_SPKOUTL_SC 44 #define MADERA_IRQ_SPKOUTR_SC 45 #define MADERA_IRQ_HP1L_ENABLE_DONE 46 #define MADERA_IRQ_HP1R_ENABLE_DONE 47 #define MADERA_IRQ_HP2L_ENABLE_DONE 48 #define MADERA_IRQ_HP2R_ENABLE_DONE 49 #define MADERA_IRQ_HP3L_ENABLE_DONE 50 #define MADERA_IRQ_HP3R_ENABLE_DONE 51 #define MADERA_IRQ_SPKOUTL_ENABLE_DONE 52 #define MADERA_IRQ_SPKOUTR_ENABLE_DONE 53 #define MADERA_IRQ_SPK_SHUTDOWN 54 #define MADERA_IRQ_SPK_OVERHEAT 55 #define MADERA_IRQ_SPK_OVERHEAT_WARN 56 #define MADERA_IRQ_GPIO1 57 #define MADERA_IRQ_GPIO2 58 #define MADERA_IRQ_GPIO3 59 #define MADERA_IRQ_GPIO4 60 #define MADERA_IRQ_GPIO5 61 #define MADERA_IRQ_GPIO6 62 #define MADERA_IRQ_GPIO7 63 #define MADERA_IRQ_GPIO8 64 #define MADERA_IRQ_DSP1_BUS_ERR 65 #define MADERA_IRQ_DSP2_BUS_ERR 66 #define MADERA_IRQ_DSP3_BUS_ERR 67 #define MADERA_IRQ_DSP4_BUS_ERR 68 #define MADERA_IRQ_DSP5_BUS_ERR 69 #define MADERA_IRQ_DSP6_BUS_ERR 70 #define MADERA_IRQ_DSP7_BUS_ERR 71 #define MADERA_NUM_IRQ 72 /* * These wrapper functions are for use by other child drivers of the * same parent MFD. */ static inline int madera_get_irq_mapping(struct madera *madera, int irq) { if (!madera->irq_dev) return -ENODEV; return regmap_irq_get_virq(madera->irq_data, irq); } static inline int madera_request_irq(struct madera *madera, int irq, const char *name, irq_handler_t handler, void *data) { irq = madera_get_irq_mapping(madera, irq); if (irq < 0) return irq; return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT, name, data); } static inline void madera_free_irq(struct madera *madera, int irq, void *data) { irq = madera_get_irq_mapping(madera, irq); if (irq < 0) return; free_irq(irq, data); } static inline int madera_set_irq_wake(struct madera *madera, int irq, int on) { irq = madera_get_irq_mapping(madera, irq); if (irq < 0) return irq; return irq_set_irq_wake(irq, on); } #endif PK Nt�ZFS�� � irq-davinci-aintc.hnu �[��� /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2019 Texas Instruments */ #ifndef _LINUX_IRQ_DAVINCI_AINTC_ #define _LINUX_IRQ_DAVINCI_AINTC_ #include <linux/ioport.h> /** * struct davinci_aintc_config - configuration data for davinci-aintc driver. * * @reg: register range to map * @num_irqs: number of HW interrupts supported by the controller * @prios: an array of size num_irqs containing priority settings for * each interrupt */ struct davinci_aintc_config { struct resource reg; unsigned int num_irqs; u8 *prios; }; void davinci_aintc_init(const struct davinci_aintc_config *config); #endif /* _LINUX_IRQ_DAVINCI_AINTC_ */ PK �Z��M1E 1E irq-madera.konu �[��� PK Nt�Zc|]�r r nE arm-gic-common.hnu �[��� PK Nt�Z�� � H arm-gic.hnu �[��� PK Nt�Z I�� � �] irq-bcm2836.hnu �[��� PK Nt�ZJk�̛ � �e mmp.hnu �[��� PK Nt�Zۜ��d d �f irq-sa11x0.hnu �[��� PK Nt�ZҸ� ,h irq-ixp4xx.hnu �[��� PK Nt�Z����7 7 |i irq-omap-intc.hnu �[��� PK Nt�Z�`��a a �k versatile-fpga.hnu �[��� PK Nt�Z����� � �m arm-vgic-info.hnu �[��� PK Nt�Z�L� _ _ �q arm-gic-v3.hnu �[��� PK Nt�Z�x2h h � irq-davinci-cp-intc.hnu �[��� PK Nt�Z�' �� xtensa-pic.hnu �[��� PK Nt�Z���>� � � chained_irq.hnu �[��� PK Nt�ZACR6 6 �� arm-gic-v4.hnu �[��� PK Nt�Z�"D�K K R� irq-partition-percpu.hnu �[��� PK Nt�Z�2ba a �� arm-vic.hnu �[��� PK Nt�Z�f6� � }� mxs.hnu �[��� PK Nt�Z�*� � �� xtensa-mx.hnu �[��� PK Nt�Z���ա � �� irq-madera.hnu �[��� PK Nt�ZFS�� � z irq-davinci-aintc.hnu �[��� PK R _
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