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PK��5^�Z k�4r ��r �� gpio-au1300.hnu��[��/* SPDX-License-Identifier: GPL-2.0 / / * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. * * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com> / #ifndef _GPIO_AU1300_H_ #define _GPIO_AU1300_H_ #include <asm/addrspace.h> #include <asm/io.h> #include <asm/mach-au1x00/au1000.h> struct gpio; struct gpio_chip; / with the current GPIC design, up to 128 GPIOs are possible. * The only implementation so far is in the Au1300, which has 75 externally * available GPIOs. / #define AU1300_GPIO_BASE 0 #define AU1300_GPIO_NUM 75 #define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) #define AU1300_GPIC_ADDR \ (void __iomem )KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) static inline int au1300_gpio_get_value(unsigned int gpio) { void __iomem roff = AU1300_GPIC_ADDR; int bit; gpio -= AU1300_GPIO_BASE; roff += GPIC_GPIO_BANKOFF(gpio); bit = GPIC_GPIO_TO_BIT(gpio); return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; } static inline int au1300_gpio_direction_input(unsigned int gpio) { void __iomem roff = AU1300_GPIC_ADDR; unsigned long bit; gpio -= AU1300_GPIO_BASE; roff += GPIC_GPIO_BANKOFF(gpio); bit = GPIC_GPIO_TO_BIT(gpio); __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); wmb(); return 0; } static inline int au1300_gpio_set_value(unsigned int gpio, int v) { void __iomem roff = AU1300_GPIC_ADDR; unsigned long bit; gpio -= AU1300_GPIO_BASE; roff += GPIC_GPIO_BANKOFF(gpio); bit = GPIC_GPIO_TO_BIT(gpio); __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL : AU1300_GPIC_PINVALCLR)); wmb(); return 0; } static inline int au1300_gpio_direction_output(unsigned int gpio, int v) { / hw switches to output automatically / return au1300_gpio_set_value(gpio, v); } static inline int au1300_gpio_to_irq(unsigned int gpio) { return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); } static inline int au1300_irq_to_gpio(unsigned int irq) { return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; } static inline int au1300_gpio_is_valid(unsigned int gpio) { int ret; switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1300: ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); break; default: ret = 0; } return ret; } static inline int au1300_gpio_cansleep(unsigned int gpio) { return 0; } / hardware remembers gpio 0-63 levels on powerup / static inline int au1300_gpio_getinitlvl(unsigned int gpio) { void __iomem roff = AU1300_GPIC_ADDR; unsigned long v; if (unlikely(gpio > 63)) return 0; else if (gpio > 31) { gpio -= 32; roff += 4; } v = __raw_readl(roff + AU1300_GPIC_RSTVAL); return (v >> gpio) & 1; } #endif /* _GPIO_AU1300_H_ / PK��5^�ZW 2��au1550_spi.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure / #ifndef _AU1550_SPI_H_ #define _AU1550_SPI_H_ struct au1550_spi_info { u32 mainclk_hz; / main input clock frequency of PSC / u16 num_chipselect; / number of chipselects supported / void (activate_cs)(struct au1550_spi_info spi, int cs, int polarity); void (deactivate_cs)(struct au1550_spi_info spi, int cs, int polarity); }; #endif PK��5^�Z�/�E�4��4��au1xxx_dbdma.hnu��[��/ * * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1550 Descriptor * Based DMA Controller. * * Copyright 2004 Embedded Edge, LLC * dan@embeddededge.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. / / * Specifics for the Au1xxx Descriptor-Based DMA Controller, * first seen in the AU1550 part. / #ifndef _AU1000_DBDMA_H_ #define _AU1000_DBDMA_H_ #ifndef _LANGUAGE_ASSEMBLY typedef volatile struct dbdma_global { u32 ddma_config; u32 ddma_intstat; u32 ddma_throttle; u32 ddma_inten; } dbdma_global_t; / General Configuration. / #define DDMA_CONFIG_AF (1 << 2) #define DDMA_CONFIG_AH (1 << 1) #define DDMA_CONFIG_AL (1 << 0) #define DDMA_THROTTLE_EN (1 << 31) / The structure of a DMA Channel. / typedef volatile struct au1xxx_dma_channel { u32 ddma_cfg; / See below / u32 ddma_desptr; / 32-byte aligned pointer to descriptor / u32 ddma_statptr; / word aligned pointer to status word / u32 ddma_dbell; / A write activates channel operation / u32 ddma_irq; / If bit 0 set, interrupt pending / u32 ddma_stat; / See below / u32 ddma_bytecnt; / Byte count, valid only when chan idle / / Remainder, up to the 256 byte boundary, is reserved. / } au1x_dma_chan_t; #define DDMA_CFG_SED (1 << 9) / source DMA level/edge detect / #define DDMA_CFG_SP (1 << 8) / source DMA polarity / #define DDMA_CFG_DED (1 << 7) / destination DMA level/edge detect / #define DDMA_CFG_DP (1 << 6) / destination DMA polarity / #define DDMA_CFG_SYNC (1 << 5) / Sync static bus controller / #define DDMA_CFG_PPR (1 << 4) / PCI posted read/write control / #define DDMA_CFG_DFN (1 << 3) / Descriptor fetch non-coherent / #define DDMA_CFG_SBE (1 << 2) / Source big endian / #define DDMA_CFG_DBE (1 << 1) / Destination big endian / #define DDMA_CFG_EN (1 << 0) / Channel enable / / * Always set when descriptor processing done, regardless of * interrupt enable state. Reflected in global intstat, don't * clear this until global intstat is read/used. / #define DDMA_IRQ_IN (1 << 0) #define DDMA_STAT_DB (1 << 2) / Doorbell pushed / #define DDMA_STAT_V (1 << 1) / Descriptor valid / #define DDMA_STAT_H (1 << 0) / Channel Halted / / * "Standard" DDMA Descriptor. * Must be 32-byte aligned. / typedef volatile struct au1xxx_ddma_desc { u32 dscr_cmd0; / See below / u32 dscr_cmd1; / See below / u32 dscr_source0; / source phys address / u32 dscr_source1; / See below / u32 dscr_dest0; / Destination address / u32 dscr_dest1; / See below / u32 dscr_stat; / completion status / u32 dscr_nxtptr; / Next descriptor pointer (mostly) / / * First 32 bytes are HW specific!!! * Let's have some SW data following -- make sure it's 32 bytes. / u32 sw_status; u32 sw_context; u32 sw_reserved[6]; } au1x_ddma_desc_t; #define DSCR_CMD0_V (1 << 31) / Descriptor valid / #define DSCR_CMD0_MEM (1 << 30) / mem-mem transfer / #define DSCR_CMD0_SID_MASK (0x1f << 25) / Source ID / #define DSCR_CMD0_DID_MASK (0x1f << 20) / Destination ID / #define DSCR_CMD0_SW_MASK (0x3 << 18) / Source Width / #define DSCR_CMD0_DW_MASK (0x3 << 16) / Destination Width / #define DSCR_CMD0_ARB (0x1 << 15) / Set for Hi Pri / #define DSCR_CMD0_DT_MASK (0x3 << 13) / Descriptor Type / #define DSCR_CMD0_SN (0x1 << 12) / Source non-coherent / #define DSCR_CMD0_DN (0x1 << 11) / Destination non-coherent / #define DSCR_CMD0_SM (0x1 << 10) / Stride mode / #define DSCR_CMD0_IE (0x1 << 8) / Interrupt Enable / #define DSCR_CMD0_SP (0x1 << 4) / Status pointer select / #define DSCR_CMD0_CV (0x1 << 2) / Clear Valid when done / #define DSCR_CMD0_ST_MASK (0x3 << 0) / Status instruction / #define SW_STATUS_INUSE (1 << 0) / Command 0 device IDs. / #define AU1550_DSCR_CMD0_UART0_TX 0 #define AU1550_DSCR_CMD0_UART0_RX 1 #define AU1550_DSCR_CMD0_UART3_TX 2 #define AU1550_DSCR_CMD0_UART3_RX 3 #define AU1550_DSCR_CMD0_DMA_REQ0 4 #define AU1550_DSCR_CMD0_DMA_REQ1 5 #define AU1550_DSCR_CMD0_DMA_REQ2 6 #define AU1550_DSCR_CMD0_DMA_REQ3 7 #define AU1550_DSCR_CMD0_USBDEV_RX0 8 #define AU1550_DSCR_CMD0_USBDEV_TX0 9 #define AU1550_DSCR_CMD0_USBDEV_TX1 10 #define AU1550_DSCR_CMD0_USBDEV_TX2 11 #define AU1550_DSCR_CMD0_USBDEV_RX3 12 #define AU1550_DSCR_CMD0_USBDEV_RX4 13 #define AU1550_DSCR_CMD0_PSC0_TX 14 #define AU1550_DSCR_CMD0_PSC0_RX 15 #define AU1550_DSCR_CMD0_PSC1_TX 16 #define AU1550_DSCR_CMD0_PSC1_RX 17 #define AU1550_DSCR_CMD0_PSC2_TX 18 #define AU1550_DSCR_CMD0_PSC2_RX 19 #define AU1550_DSCR_CMD0_PSC3_TX 20 #define AU1550_DSCR_CMD0_PSC3_RX 21 #define AU1550_DSCR_CMD0_PCI_WRITE 22 #define AU1550_DSCR_CMD0_NAND_FLASH 23 #define AU1550_DSCR_CMD0_MAC0_RX 24 #define AU1550_DSCR_CMD0_MAC0_TX 25 #define AU1550_DSCR_CMD0_MAC1_RX 26 #define AU1550_DSCR_CMD0_MAC1_TX 27 #define AU1200_DSCR_CMD0_UART0_TX 0 #define AU1200_DSCR_CMD0_UART0_RX 1 #define AU1200_DSCR_CMD0_UART1_TX 2 #define AU1200_DSCR_CMD0_UART1_RX 3 #define AU1200_DSCR_CMD0_DMA_REQ0 4 #define AU1200_DSCR_CMD0_DMA_REQ1 5 #define AU1200_DSCR_CMD0_MAE_BE 6 #define AU1200_DSCR_CMD0_MAE_FE 7 #define AU1200_DSCR_CMD0_SDMS_TX0 8 #define AU1200_DSCR_CMD0_SDMS_RX0 9 #define AU1200_DSCR_CMD0_SDMS_TX1 10 #define AU1200_DSCR_CMD0_SDMS_RX1 11 #define AU1200_DSCR_CMD0_AES_TX 13 #define AU1200_DSCR_CMD0_AES_RX 12 #define AU1200_DSCR_CMD0_PSC0_TX 14 #define AU1200_DSCR_CMD0_PSC0_RX 15 #define AU1200_DSCR_CMD0_PSC1_TX 16 #define AU1200_DSCR_CMD0_PSC1_RX 17 #define AU1200_DSCR_CMD0_CIM_RXA 18 #define AU1200_DSCR_CMD0_CIM_RXB 19 #define AU1200_DSCR_CMD0_CIM_RXC 20 #define AU1200_DSCR_CMD0_MAE_BOTH 21 #define AU1200_DSCR_CMD0_LCD 22 #define AU1200_DSCR_CMD0_NAND_FLASH 23 #define AU1200_DSCR_CMD0_PSC0_SYNC 24 #define AU1200_DSCR_CMD0_PSC1_SYNC 25 #define AU1200_DSCR_CMD0_CIM_SYNC 26 #define AU1300_DSCR_CMD0_UART0_TX 0 #define AU1300_DSCR_CMD0_UART0_RX 1 #define AU1300_DSCR_CMD0_UART1_TX 2 #define AU1300_DSCR_CMD0_UART1_RX 3 #define AU1300_DSCR_CMD0_UART2_TX 4 #define AU1300_DSCR_CMD0_UART2_RX 5 #define AU1300_DSCR_CMD0_UART3_TX 6 #define AU1300_DSCR_CMD0_UART3_RX 7 #define AU1300_DSCR_CMD0_SDMS_TX0 8 #define AU1300_DSCR_CMD0_SDMS_RX0 9 #define AU1300_DSCR_CMD0_SDMS_TX1 10 #define AU1300_DSCR_CMD0_SDMS_RX1 11 #define AU1300_DSCR_CMD0_AES_TX 12 #define AU1300_DSCR_CMD0_AES_RX 13 #define AU1300_DSCR_CMD0_PSC0_TX 14 #define AU1300_DSCR_CMD0_PSC0_RX 15 #define AU1300_DSCR_CMD0_PSC1_TX 16 #define AU1300_DSCR_CMD0_PSC1_RX 17 #define AU1300_DSCR_CMD0_PSC2_TX 18 #define AU1300_DSCR_CMD0_PSC2_RX 19 #define AU1300_DSCR_CMD0_PSC3_TX 20 #define AU1300_DSCR_CMD0_PSC3_RX 21 #define AU1300_DSCR_CMD0_LCD 22 #define AU1300_DSCR_CMD0_NAND_FLASH 23 #define AU1300_DSCR_CMD0_SDMS_TX2 24 #define AU1300_DSCR_CMD0_SDMS_RX2 25 #define AU1300_DSCR_CMD0_CIM_SYNC 26 #define AU1300_DSCR_CMD0_UDMA 27 #define AU1300_DSCR_CMD0_DMA_REQ0 28 #define AU1300_DSCR_CMD0_DMA_REQ1 29 #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 / This macro is used to find/create custom device types / #define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) \| 0x32000000) \| \ ((d) & 0xFF)) #define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF) #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) / Source/Destination transfer width. / #define DSCR_CMD0_BYTE 0 #define DSCR_CMD0_HALFWORD 1 #define DSCR_CMD0_WORD 2 #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) / DDMA Descriptor Type. / #define DSCR_CMD0_STANDARD 0 #define DSCR_CMD0_LITERAL 1 #define DSCR_CMD0_CMP_BRANCH 2 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) / Status Instruction. / #define DSCR_CMD0_ST_NOCHANGE 0 / Don't change / #define DSCR_CMD0_ST_CURRENT 1 / Write current status / #define DSCR_CMD0_ST_CMD0 2 / Write cmd0 with V cleared / #define DSCR_CMD0_ST_BYTECNT 3 / Write remaining byte count / #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) / Descriptor Command 1. / #define DSCR_CMD1_SUPTR_MASK (0xf << 28) / upper 4 bits of src addr / #define DSCR_CMD1_DUPTR_MASK (0xf << 24) / upper 4 bits of dest addr / #define DSCR_CMD1_FL_MASK (0x3 << 22) / Flag bits / #define DSCR_CMD1_BC_MASK (0x3fffff) / Byte count / / Flag description. / #define DSCR_CMD1_FL_MEM_STRIDE0 0 #define DSCR_CMD1_FL_MEM_STRIDE1 1 #define DSCR_CMD1_FL_MEM_STRIDE2 2 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) / Source1, 1-dimensional stride. / #define DSCR_SRC1_STS_MASK (3 << 30) / Src xfer size / #define DSCR_SRC1_SAM_MASK (3 << 28) / Src xfer movement / #define DSCR_SRC1_SB_MASK (0x3fff << 14) / Block size / #define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14) #define DSCR_SRC1_SS_MASK (0x3fff << 0) / Stride / #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) / Dest1, 1-dimensional stride. / #define DSCR_DEST1_DTS_MASK (3 << 30) / Dest xfer size / #define DSCR_DEST1_DAM_MASK (3 << 28) / Dest xfer movement / #define DSCR_DEST1_DB_MASK (0x3fff << 14) / Block size / #define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14) #define DSCR_DEST1_DS_MASK (0x3fff << 0) / Stride / #define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0) #define DSCR_xTS_SIZE1 0 #define DSCR_xTS_SIZE2 1 #define DSCR_xTS_SIZE4 2 #define DSCR_xTS_SIZE8 3 #define DSCR_SRC1_STS(x) (((x) & 3) << 30) #define DSCR_DEST1_DTS(x) (((x) & 3) << 30) #define DSCR_xAM_INCREMENT 0 #define DSCR_xAM_DECREMENT 1 #define DSCR_xAM_STATIC 2 #define DSCR_xAM_BURST 3 #define DSCR_SRC1_SAM(x) (((x) & 3) << 28) #define DSCR_DEST1_DAM(x) (((x) & 3) << 28) / The next descriptor pointer. / #define DSCR_NXTPTR_MASK (0x07ffffff) #define DSCR_NXTPTR(x) ((x) >> 5) #define DSCR_GET_NXTPTR(x) ((x) << 5) #define DSCR_NXTPTR_MS (1 << 27) / The number of DBDMA channels. / #define NUM_DBDMA_CHANS 16 / * DDMA API definitions * FIXME: may not fit to this header file / typedef struct dbdma_device_table { u32 dev_id; u32 dev_flags; u32 dev_tsize; u32 dev_devwidth; u32 dev_physaddr; / If FIFO / u32 dev_intlevel; u32 dev_intpolarity; } dbdev_tab_t; typedef struct dbdma_chan_config { spinlock_t lock; u32 chan_flags; u32 chan_index; dbdev_tab_t chan_src; dbdev_tab_t chan_dest; au1x_dma_chan_t chan_ptr; au1x_ddma_desc_t chan_desc_base; u32 cdb_membase; / kmalloc base of above / au1x_ddma_desc_t get_ptr, put_ptr, cur_ptr; void chan_callparam; void (chan_callback)(int, void ); } chan_tab_t; #define DEV_FLAGS_INUSE (1 << 0) #define DEV_FLAGS_ANYUSE (1 << 1) #define DEV_FLAGS_OUT (1 << 2) #define DEV_FLAGS_IN (1 << 3) #define DEV_FLAGS_BURSTABLE (1 << 4) #define DEV_FLAGS_SYNC (1 << 5) / end DDMA API definitions / / * External functions for drivers to use. * Use this to allocate a DBDMA channel. The device IDs are one of * the DSCR_CMD0 devices IDs, which is usually redefined to a more * meaningful name. The 'callback' is called during DMA completion * interrupt. / extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, void (callback)(int, void ), void callparam); #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS /* Set the device width of an in/out FIFO. / u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); / Allocate a ring of descriptors for DBDMA. / u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); / Put buffers on source/destination descriptors. / u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags); / Get a buffer from the destination descriptor. / u32 au1xxx_dbdma_get_dest(u32 chanid, void buf, int nbytes); void au1xxx_dbdma_stop(u32 chanid); void au1xxx_dbdma_start(u32 chanid); void au1xxx_dbdma_reset(u32 chanid); u32 au1xxx_get_dma_residue(u32 chanid); void au1xxx_dbdma_chan_free(u32 chanid); void au1xxx_dbdma_dump(u32 chanid); u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t dev); extern void au1xxx_ddma_del_device(u32 devid); void au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t dp); /* * Flags for the put_source/put_dest functions. / #define DDMA_FLAGS_IE (1 << 0) #define DDMA_FLAGS_NOIE (1 << 1) #endif / _LANGUAGE_ASSEMBLY / #endif / _AU1000_DBDMA_H_ / PK��5^�Z�}td��d��au1100_mmc.hnu��[��/ * BRIEF MODULE DESCRIPTION * Defines for using the MMC/SD controllers on the * Alchemy Au1100 mips processor. * * Copyright (c) 2003 Embedded Edge, LLC. * Author: Embedded Edge, LLC. * dan@embeddededge.com or tim@embeddededge.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. * / / * AU1100 MMC/SD definitions. * * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary" * June, 2003 / #ifndef __ASM_AU1100_MMC_H #define __ASM_AU1100_MMC_H #include <linux/leds.h> struct au1xmmc_platform_data { int(cd_setup)(void mmc_host, int on); int(card_inserted)(void mmc_host); int(card_readonly)(void mmc_host); void(set_power)(void mmc_host, int state); struct led_classdev led; unsigned long mask_host_caps; }; #define SD0_BASE 0xB0600000 #define SD1_BASE 0xB0680000 /* * Register offsets. / #define SD_TXPORT (0x0000) #define SD_RXPORT (0x0004) #define SD_CONFIG (0x0008) #define SD_ENABLE (0x000C) #define SD_CONFIG2 (0x0010) #define SD_BLKSIZE (0x0014) #define SD_STATUS (0x0018) #define SD_DEBUG (0x001C) #define SD_CMD (0x0020) #define SD_CMDARG (0x0024) #define SD_RESP3 (0x0028) #define SD_RESP2 (0x002C) #define SD_RESP1 (0x0030) #define SD_RESP0 (0x0034) #define SD_TIMEOUT (0x0038) / * SD_TXPORT bit definitions. / #define SD_TXPORT_TXD (0x000000ff) / * SD_RXPORT bit definitions. / #define SD_RXPORT_RXD (0x000000ff) / * SD_CONFIG bit definitions. / #define SD_CONFIG_DIV (0x000001ff) #define SD_CONFIG_DE (0x00000200) #define SD_CONFIG_NE (0x00000400) #define SD_CONFIG_TU (0x00000800) #define SD_CONFIG_TO (0x00001000) #define SD_CONFIG_RU (0x00002000) #define SD_CONFIG_RO (0x00004000) #define SD_CONFIG_I (0x00008000) #define SD_CONFIG_CR (0x00010000) #define SD_CONFIG_RAT (0x00020000) #define SD_CONFIG_DD (0x00040000) #define SD_CONFIG_DT (0x00080000) #define SD_CONFIG_SC (0x00100000) #define SD_CONFIG_RC (0x00200000) #define SD_CONFIG_WC (0x00400000) #define SD_CONFIG_xxx (0x00800000) #define SD_CONFIG_TH (0x01000000) #define SD_CONFIG_TE (0x02000000) #define SD_CONFIG_TA (0x04000000) #define SD_CONFIG_RH (0x08000000) #define SD_CONFIG_RA (0x10000000) #define SD_CONFIG_RF (0x20000000) #define SD_CONFIG_CD (0x40000000) #define SD_CONFIG_SI (0x80000000) / * SD_ENABLE bit definitions. / #define SD_ENABLE_CE (0x00000001) #define SD_ENABLE_R (0x00000002) / * SD_CONFIG2 bit definitions. / #define SD_CONFIG2_EN (0x00000001) #define SD_CONFIG2_FF (0x00000002) #define SD_CONFIG2_xx1 (0x00000004) #define SD_CONFIG2_DF (0x00000008) #define SD_CONFIG2_DC (0x00000010) #define SD_CONFIG2_xx2 (0x000000e0) #define SD_CONFIG2_BB (0x00000080) #define SD_CONFIG2_WB (0x00000100) #define SD_CONFIG2_RW (0x00000200) #define SD_CONFIG2_DP (0x00000400) / * SD_BLKSIZE bit definitions. / #define SD_BLKSIZE_BS (0x000007ff) #define SD_BLKSIZE_BS_SHIFT (0) #define SD_BLKSIZE_BC (0x01ff0000) #define SD_BLKSIZE_BC_SHIFT (16) / * SD_STATUS bit definitions. / #define SD_STATUS_DCRCW (0x00000007) #define SD_STATUS_xx1 (0x00000008) #define SD_STATUS_CB (0x00000010) #define SD_STATUS_DB (0x00000020) #define SD_STATUS_CF (0x00000040) #define SD_STATUS_D3 (0x00000080) #define SD_STATUS_xx2 (0x00000300) #define SD_STATUS_NE (0x00000400) #define SD_STATUS_TU (0x00000800) #define SD_STATUS_TO (0x00001000) #define SD_STATUS_RU (0x00002000) #define SD_STATUS_RO (0x00004000) #define SD_STATUS_I (0x00008000) #define SD_STATUS_CR (0x00010000) #define SD_STATUS_RAT (0x00020000) #define SD_STATUS_DD (0x00040000) #define SD_STATUS_DT (0x00080000) #define SD_STATUS_SC (0x00100000) #define SD_STATUS_RC (0x00200000) #define SD_STATUS_WC (0x00400000) #define SD_STATUS_xx3 (0x00800000) #define SD_STATUS_TH (0x01000000) #define SD_STATUS_TE (0x02000000) #define SD_STATUS_TA (0x04000000) #define SD_STATUS_RH (0x08000000) #define SD_STATUS_RA (0x10000000) #define SD_STATUS_RF (0x20000000) #define SD_STATUS_CD (0x40000000) #define SD_STATUS_SI (0x80000000) / * SD_CMD bit definitions. / #define SD_CMD_GO (0x00000001) #define SD_CMD_RY (0x00000002) #define SD_CMD_xx1 (0x0000000c) #define SD_CMD_CT_MASK (0x000000f0) #define SD_CMD_CT_0 (0x00000000) #define SD_CMD_CT_1 (0x00000010) #define SD_CMD_CT_2 (0x00000020) #define SD_CMD_CT_3 (0x00000030) #define SD_CMD_CT_4 (0x00000040) #define SD_CMD_CT_5 (0x00000050) #define SD_CMD_CT_6 (0x00000060) #define SD_CMD_CT_7 (0x00000070) #define SD_CMD_CI (0x0000ff00) #define SD_CMD_CI_SHIFT (8) #define SD_CMD_RT_MASK (0x00ff0000) #define SD_CMD_RT_0 (0x00000000) #define SD_CMD_RT_1 (0x00010000) #define SD_CMD_RT_2 (0x00020000) #define SD_CMD_RT_3 (0x00030000) #define SD_CMD_RT_4 (0x00040000) #define SD_CMD_RT_5 (0x00050000) #define SD_CMD_RT_6 (0x00060000) #define SD_CMD_RT_1B (0x00810000) #endif / __ASM_AU1100_MMC_H / PK��5^�Z��I4��4�� au1550nd.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * platform data for the Au1550 NAND driver / #ifndef _AU1550ND_H_ #define _AU1550ND_H_ #include <linux/mtd/partitions.h> struct au1550nd_platdata { struct mtd_partition parts; int num_parts; int devwidth; /* 0 = 8bit device, 1 = 16bit device / }; #endif PK��5^�Z��a]c6��c6�� gpio-au1000.hnu��[��/ * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200 * * Copyright (c) 2009 Manuel Lauss. * * Licensed under the terms outlined in the file COPYING. / #ifndef _ALCHEMY_GPIO_AU1000_H_ #define _ALCHEMY_GPIO_AU1000_H_ #include <asm/mach-au1x00/au1000.h> / The default GPIO numberspace as documented in the Alchemy manuals. * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. / #define ALCHEMY_GPIO1_BASE 0 #define ALCHEMY_GPIO2_BASE 200 #define ALCHEMY_GPIO1_NUM 32 #define ALCHEMY_GPIO2_NUM 16 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1) #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) / GPIO1 registers within SYS_ area / #define AU1000_SYS_TRIOUTRD 0x100 #define AU1000_SYS_TRIOUTCLR 0x100 #define AU1000_SYS_OUTPUTRD 0x108 #define AU1000_SYS_OUTPUTSET 0x108 #define AU1000_SYS_OUTPUTCLR 0x10C #define AU1000_SYS_PINSTATERD 0x110 #define AU1000_SYS_PININPUTEN 0x110 / register offsets within GPIO2 block / #define AU1000_GPIO2_DIR 0x00 #define AU1000_GPIO2_OUTPUT 0x08 #define AU1000_GPIO2_PINSTATE 0x0C #define AU1000_GPIO2_INTENABLE 0x10 #define AU1000_GPIO2_ENABLE 0x14 struct gpio; static inline int au1000_gpio1_to_irq(int gpio) { return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); } static inline int au1000_gpio2_to_irq(int gpio) { return -ENXIO; } static inline int au1000_irq_to_gpio(int irq) { if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT)) return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; return -ENXIO; } static inline int au1500_gpio1_to_irq(int gpio) { gpio -= ALCHEMY_GPIO1_BASE; switch (gpio) { case 0 ... 15: case 20: case 23 ... 28: return MAKE_IRQ(1, gpio); } return -ENXIO; } static inline int au1500_gpio2_to_irq(int gpio) { gpio -= ALCHEMY_GPIO2_BASE; switch (gpio) { case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0); case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4); case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); } return -ENXIO; } static inline int au1500_irq_to_gpio(int irq) { switch (irq) { case AU1500_GPIO0_INT ... AU1500_GPIO15_INT: case AU1500_GPIO20_INT: case AU1500_GPIO23_INT ... AU1500_GPIO28_INT: return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0; case AU1500_GPIO200_INT ... AU1500_GPIO203_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0; case AU1500_GPIO204_INT ... AU1500_GPIO205_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4; case AU1500_GPIO206_INT ... AU1500_GPIO207_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6; case AU1500_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + 8; } return -ENXIO; } static inline int au1100_gpio1_to_irq(int gpio) { return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); } static inline int au1100_gpio2_to_irq(int gpio) { gpio -= ALCHEMY_GPIO2_BASE; if ((gpio >= 8) && (gpio <= 15)) return MAKE_IRQ(0, 29); / shared GPIO208_215 / return -ENXIO; } static inline int au1100_irq_to_gpio(int irq) { switch (irq) { case AU1100_GPIO0_INT ... AU1100_GPIO31_INT: return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0; case AU1100_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + 8; } return -ENXIO; } static inline int au1550_gpio1_to_irq(int gpio) { gpio -= ALCHEMY_GPIO1_BASE; switch (gpio) { case 0 ... 15: case 20 ... 28: return MAKE_IRQ(1, gpio); case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); } return -ENXIO; } static inline int au1550_gpio2_to_irq(int gpio) { gpio -= ALCHEMY_GPIO2_BASE; switch (gpio) { case 0: return MAKE_IRQ(1, 16); case 1 ... 5: return MAKE_IRQ(1, 17); / shared GPIO201_205 / case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); case 8 ... 15: return MAKE_IRQ(1, 31); / shared GPIO208_215 / } return -ENXIO; } static inline int au1550_irq_to_gpio(int irq) { switch (irq) { case AU1550_GPIO0_INT ... AU1550_GPIO15_INT: return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0; case AU1550_GPIO200_INT: case AU1550_GPIO201_205_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0; case AU1550_GPIO16_INT ... AU1550_GPIO28_INT: return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16; case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6; } return -ENXIO; } static inline int au1200_gpio1_to_irq(int gpio) { return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); } static inline int au1200_gpio2_to_irq(int gpio) { gpio -= ALCHEMY_GPIO2_BASE; switch (gpio) { case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0); case 3: return MAKE_IRQ(0, 22); case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4); case 8 ... 15: return MAKE_IRQ(0, 28); / shared GPIO208_215 / } return -ENXIO; } static inline int au1200_irq_to_gpio(int irq) { switch (irq) { case AU1200_GPIO0_INT ... AU1200_GPIO31_INT: return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0; case AU1200_GPIO200_INT ... AU1200_GPIO202_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0; case AU1200_GPIO203_INT: return ALCHEMY_GPIO2_BASE + 3; case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT: return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4; } return -ENXIO; } / * GPIO1 block macros for common linux gpio functions. / static inline void alchemy_gpio1_set_value(int gpio, int v) { unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR; alchemy_wrsys(mask, r); } static inline int alchemy_gpio1_get_value(int gpio) { unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask; } static inline int alchemy_gpio1_direction_input(int gpio) { unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR); return 0; } static inline int alchemy_gpio1_direction_output(int gpio, int v) { / hardware switches to "output" mode when one of the two * "set_value" registers is accessed. / alchemy_gpio1_set_value(gpio, v); return 0; } static inline int alchemy_gpio1_is_valid(int gpio) { return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX)); } static inline int alchemy_gpio1_to_irq(int gpio) { switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000: return au1000_gpio1_to_irq(gpio); case ALCHEMY_CPU_AU1100: return au1100_gpio1_to_irq(gpio); case ALCHEMY_CPU_AU1500: return au1500_gpio1_to_irq(gpio); case ALCHEMY_CPU_AU1550: return au1550_gpio1_to_irq(gpio); case ALCHEMY_CPU_AU1200: return au1200_gpio1_to_irq(gpio); } return -ENXIO; } / On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this * register enables use of GPIOs as wake source. / static inline void alchemy_gpio1_input_enable(void) { void __iomem base = (void __iomem )KSEG1ADDR(AU1000_SYS_PHYS_ADDR); __raw_writel(0, base + 0x110); / the write op is key / wmb(); } / * GPIO2 block macros for common linux GPIO functions. The 'gpio' * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX. / static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); if (to_out) d \|= mask; else d &= ~mask; __raw_writel(d, base + AU1000_GPIO2_DIR); wmb(); } static inline void alchemy_gpio2_set_value(int gpio, int v) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); unsigned long mask; mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); wmb(); } static inline int alchemy_gpio2_get_value(int gpio) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); return __raw_readl(base + AU1000_GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); } static inline int alchemy_gpio2_direction_input(int gpio) { unsigned long flags; local_irq_save(flags); __alchemy_gpio2_mod_dir(gpio, 0); local_irq_restore(flags); return 0; } static inline int alchemy_gpio2_direction_output(int gpio, int v) { unsigned long flags; alchemy_gpio2_set_value(gpio, v); local_irq_save(flags); __alchemy_gpio2_mod_dir(gpio, 1); local_irq_restore(flags); return 0; } static inline int alchemy_gpio2_is_valid(int gpio) { return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX)); } static inline int alchemy_gpio2_to_irq(int gpio) { switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000: return au1000_gpio2_to_irq(gpio); case ALCHEMY_CPU_AU1100: return au1100_gpio2_to_irq(gpio); case ALCHEMY_CPU_AU1500: return au1500_gpio2_to_irq(gpio); case ALCHEMY_CPU_AU1550: return au1550_gpio2_to_irq(gpio); case ALCHEMY_CPU_AU1200: return au1200_gpio2_to_irq(gpio); } return -ENXIO; } /********************************************************************/ / GPIO2 shared interrupts and control / static inline void __alchemy_gpio2_mod_int(int gpio2, int en) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE); if (en) r \|= 1 << gpio2; else r &= ~(1 << gpio2); __raw_writel(r, base + AU1000_GPIO2_INTENABLE); wmb(); } /* * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution. * @gpio2: The GPIO2 pin to activate (200...215). * * GPIO208-215 have one shared interrupt line to the INTC. They are * and'ed with a per-pin enable bit and finally or'ed together to form * a single irq request (useful for active-high sources). * With this function, a pins' individual contribution to the int request * can be enabled. As with all other GPIO-based interrupts, the INTC * must be programmed to accept the GPIO208_215 interrupt as well. * * NOTE: Calling this macro is only necessary for GPIO208-215; all other * GPIO2-based interrupts have their own request to the INTC. Please * consult your Alchemy databook for more information! * * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request * line to the INTC, GPIO201_205. This function can be used for those * as well. * * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace * (200-215 by default). No sanity checks are made, / static inline void alchemy_gpio2_enable_int(int gpio2) { unsigned long flags; gpio2 -= ALCHEMY_GPIO2_BASE; / Au1100/Au1500 have GPIO208-215 enable bits at 0..7 / switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1100: case ALCHEMY_CPU_AU1500: gpio2 -= 8; } local_irq_save(flags); __alchemy_gpio2_mod_int(gpio2, 1); local_irq_restore(flags); } /* * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution. * @gpio2: The GPIO2 pin to activate (200...215). * * see function alchemy_gpio2_enable_int() for more information. / static inline void alchemy_gpio2_disable_int(int gpio2) { unsigned long flags; gpio2 -= ALCHEMY_GPIO2_BASE; / Au1100/Au1500 have GPIO208-215 enable bits at 0..7 / switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1100: case ALCHEMY_CPU_AU1500: gpio2 -= 8; } local_irq_save(flags); __alchemy_gpio2_mod_int(gpio2, 0); local_irq_restore(flags); } /* * alchemy_gpio2_enable - Activate GPIO2 block. * * The GPIO2 block must be enabled excplicitly to work. On systems * where this isn't done by the bootloader, this macro can be used. / static inline void alchemy_gpio2_enable(void) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); __raw_writel(3, base + AU1000_GPIO2_ENABLE); / reset, clock enabled / wmb(); __raw_writel(1, base + AU1000_GPIO2_ENABLE); / clock enabled / wmb(); } /* * alchemy_gpio2_disable - disable GPIO2 block. * * Disable and put GPIO2 block in low-power mode. / static inline void alchemy_gpio2_disable(void) { void __iomem base = (void __iomem )KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); __raw_writel(2, base + AU1000_GPIO2_ENABLE); / reset, clock disabled / wmb(); } /********************************************************************/ / wrappers for on-chip gpios; can be used before gpio chips have been * registered with gpiolib. / static inline int alchemy_gpio_direction_input(int gpio) { return (gpio >= ALCHEMY_GPIO2_BASE) ? alchemy_gpio2_direction_input(gpio) : alchemy_gpio1_direction_input(gpio); } static inline int alchemy_gpio_direction_output(int gpio, int v) { return (gpio >= ALCHEMY_GPIO2_BASE) ? alchemy_gpio2_direction_output(gpio, v) : alchemy_gpio1_direction_output(gpio, v); } static inline int alchemy_gpio_get_value(int gpio) { return (gpio >= ALCHEMY_GPIO2_BASE) ? alchemy_gpio2_get_value(gpio) : alchemy_gpio1_get_value(gpio); } static inline void alchemy_gpio_set_value(int gpio, int v) { if (gpio >= ALCHEMY_GPIO2_BASE) alchemy_gpio2_set_value(gpio, v); else alchemy_gpio1_set_value(gpio, v); } static inline int alchemy_gpio_is_valid(int gpio) { return (gpio >= ALCHEMY_GPIO2_BASE) ? alchemy_gpio2_is_valid(gpio) : alchemy_gpio1_is_valid(gpio); } static inline int alchemy_gpio_cansleep(int gpio) { return 0; / Alchemy never gets tired / } static inline int alchemy_gpio_to_irq(int gpio) { return (gpio >= ALCHEMY_GPIO2_BASE) ? alchemy_gpio2_to_irq(gpio) : alchemy_gpio1_to_irq(gpio); } static inline int alchemy_irq_to_gpio(int irq) { switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000: return au1000_irq_to_gpio(irq); case ALCHEMY_CPU_AU1100: return au1100_irq_to_gpio(irq); case ALCHEMY_CPU_AU1500: return au1500_irq_to_gpio(irq); case ALCHEMY_CPU_AU1550: return au1550_irq_to_gpio(irq); case ALCHEMY_CPU_AU1200: return au1200_irq_to_gpio(irq); } return -ENXIO; } #endif / _ALCHEMY_GPIO_AU1000_H_ / PK��5^�Z_��5��5��au1000.hnu��[��/ * * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. <source@mvista.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. / / * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp / #ifndef _AU1000_H_ #define _AU1000_H_ / SOC Interrupt numbers / / Au1000-style (IC0/1): 2 controllers with 32 sources each / #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST / Au1300-style (GPIC): 1 controller with up to 128 sources / #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define ALCHEMY_GPIC_INT_NUM 128 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) / common clock names, shared among all variants. AUXPLL2 is Au1300 / #define ALCHEMY_ROOT_CLK "root_clk" #define ALCHEMY_CPU_CLK "cpu_clk" #define ALCHEMY_AUXPLL_CLK "auxpll_clk" #define ALCHEMY_AUXPLL2_CLK "auxpll2_clk" #define ALCHEMY_SYSBUS_CLK "sysbus_clk" #define ALCHEMY_PERIPH_CLK "periph_clk" #define ALCHEMY_MEM_CLK "mem_clk" #define ALCHEMY_LR_CLK "lr_clk" #define ALCHEMY_FG0_CLK "fg0_clk" #define ALCHEMY_FG1_CLK "fg1_clk" #define ALCHEMY_FG2_CLK "fg2_clk" #define ALCHEMY_FG3_CLK "fg3_clk" #define ALCHEMY_FG4_CLK "fg4_clk" #define ALCHEMY_FG5_CLK "fg5_clk" / Au1300 peripheral interrupt numbers / #define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) #define AU1300_UART1_INT (AU1300_FIRST_INT + 17) #define AU1300_UART2_INT (AU1300_FIRST_INT + 25) #define AU1300_UART3_INT (AU1300_FIRST_INT + 27) #define AU1300_SD1_INT (AU1300_FIRST_INT + 32) #define AU1300_SD2_INT (AU1300_FIRST_INT + 38) #define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) #define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) #define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) #define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) #define AU1300_NAND_INT (AU1300_FIRST_INT + 62) #define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) #define AU1300_MMU_INT (AU1300_FIRST_INT + 76) #define AU1300_MPU_INT (AU1300_FIRST_INT + 77) #define AU1300_GPU_INT (AU1300_FIRST_INT + 78) #define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) #define AU1300_TOY_INT (AU1300_FIRST_INT + 80) #define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) #define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) #define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) #define AU1300_RTC_INT (AU1300_FIRST_INT + 84) #define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) #define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) #define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) #define AU1300_UART0_INT (AU1300_FIRST_INT + 88) #define AU1300_SD0_INT (AU1300_FIRST_INT + 89) #define AU1300_USB_INT (AU1300_FIRST_INT + 90) #define AU1300_LCD_INT (AU1300_FIRST_INT + 91) #define AU1300_BSA_INT (AU1300_FIRST_INT + 92) #define AU1300_MPE_INT (AU1300_FIRST_INT + 93) #define AU1300_ITE_INT (AU1300_FIRST_INT + 94) #define AU1300_AES_INT (AU1300_FIRST_INT + 95) #define AU1300_CIM_INT (AU1300_FIRST_INT + 96) /********************************************************************/ / * Physical base addresses for integrated peripherals * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 / #define AU1000_AC97_PHYS_ADDR 0x10000000 / 012 / #define AU1300_ROM_PHYS_ADDR 0x10000000 / 5 / #define AU1300_OTP_PHYS_ADDR 0x10002000 / 5 / #define AU1300_VSS_PHYS_ADDR 0x10003000 / 5 / #define AU1300_UART0_PHYS_ADDR 0x10100000 / 5 / #define AU1300_UART1_PHYS_ADDR 0x10101000 / 5 / #define AU1300_UART2_PHYS_ADDR 0x10102000 / 5 / #define AU1300_UART3_PHYS_ADDR 0x10103000 / 5 / #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 / 012 / #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 / 0123 / #define AU1300_GPIC_PHYS_ADDR 0x10200000 / 5 / #define AU1000_IRDA_PHYS_ADDR 0x10300000 / 02 / #define AU1200_AES_PHYS_ADDR 0x10300000 / 45 / #define AU1000_IC0_PHYS_ADDR 0x10400000 / 01234 / #define AU1300_GPU_PHYS_ADDR 0x10500000 / 5 / #define AU1000_MAC0_PHYS_ADDR 0x10500000 / 023 / #define AU1000_MAC1_PHYS_ADDR 0x10510000 / 023 / #define AU1000_MACEN_PHYS_ADDR 0x10520000 / 023 / #define AU1100_SD0_PHYS_ADDR 0x10600000 / 245 / #define AU1300_SD1_PHYS_ADDR 0x10601000 / 5 / #define AU1300_SD2_PHYS_ADDR 0x10602000 / 5 / #define AU1100_SD1_PHYS_ADDR 0x10680000 / 24 / #define AU1300_SYS_PHYS_ADDR 0x10900000 / 5 / #define AU1550_PSC2_PHYS_ADDR 0x10A00000 / 3 / #define AU1550_PSC3_PHYS_ADDR 0x10B00000 / 3 / #define AU1300_PSC0_PHYS_ADDR 0x10A00000 / 5 / #define AU1300_PSC1_PHYS_ADDR 0x10A01000 / 5 / #define AU1300_PSC2_PHYS_ADDR 0x10A02000 / 5 / #define AU1300_PSC3_PHYS_ADDR 0x10A03000 / 5 / #define AU1000_I2S_PHYS_ADDR 0x11000000 / 02 / #define AU1500_MAC0_PHYS_ADDR 0x11500000 / 1 / #define AU1500_MAC1_PHYS_ADDR 0x11510000 / 1 / #define AU1500_MACEN_PHYS_ADDR 0x11520000 / 1 / #define AU1000_UART0_PHYS_ADDR 0x11100000 / 01234 / #define AU1200_SWCNT_PHYS_ADDR 0x1110010C / 4 / #define AU1000_UART1_PHYS_ADDR 0x11200000 / 0234 / #define AU1000_UART2_PHYS_ADDR 0x11300000 / 0 / #define AU1000_UART3_PHYS_ADDR 0x11400000 / 0123 / #define AU1000_SSI0_PHYS_ADDR 0x11600000 / 02 / #define AU1000_SSI1_PHYS_ADDR 0x11680000 / 02 / #define AU1500_GPIO2_PHYS_ADDR 0x11700000 / 1234 / #define AU1000_IC1_PHYS_ADDR 0x11800000 / 01234 / #define AU1000_SYS_PHYS_ADDR 0x11900000 / 012345 / #define AU1550_PSC0_PHYS_ADDR 0x11A00000 / 34 / #define AU1550_PSC1_PHYS_ADDR 0x11B00000 / 34 / #define AU1000_MEM_PHYS_ADDR 0x14000000 / 01234 / #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 / 01234 / #define AU1300_UDMA_PHYS_ADDR 0x14001800 / 5 / #define AU1000_DMA_PHYS_ADDR 0x14002000 / 012 / #define AU1550_DBDMA_PHYS_ADDR 0x14002000 / 345 / #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 / 345 / #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 / 0123 / #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 / 0123 / #define AU1200_CIM_PHYS_ADDR 0x14004000 / 45 / #define AU1500_PCI_PHYS_ADDR 0x14005000 / 13 / #define AU1550_PE_PHYS_ADDR 0x14008000 / 3 / #define AU1200_MAEBE_PHYS_ADDR 0x14010000 / 4 / #define AU1200_MAEFE_PHYS_ADDR 0x14012000 / 4 / #define AU1300_MAEITE_PHYS_ADDR 0x14010000 / 5 / #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 / 5 / #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 / 3 / #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 / 4 / #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 / 4 / #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 / 4 / #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 / 4 / #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 / 4 / #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 / 5 / #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 / 5 / #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 / 5 / #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 / 5 / #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 / 5 / #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 / 5 / #define AU1100_LCD_PHYS_ADDR 0x15000000 / 2 / #define AU1200_LCD_PHYS_ADDR 0x15000000 / 45 / #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL / 13 / #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL / 13 / #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL / 13 / #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL / 13 / #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL / 012345 / #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL / 012345 / #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL / 012345 / /********************************************************************/ / * Au1300 GPIO+INT controller (GPIC) register offsets and bits * Registers are 128bits (0x10 bytes), divided into 4 "banks". / #define AU1300_GPIC_PINVAL 0x0000 #define AU1300_GPIC_PINVALCLR 0x0010 #define AU1300_GPIC_IPEND 0x0020 #define AU1300_GPIC_PRIENC 0x0030 #define AU1300_GPIC_IEN 0x0040 / int_mask in manual / #define AU1300_GPIC_IDIS 0x0050 / int_maskclr in manual / #define AU1300_GPIC_DMASEL 0x0060 #define AU1300_GPIC_DEVSEL 0x0080 #define AU1300_GPIC_DEVCLR 0x0090 #define AU1300_GPIC_RSTVAL 0x00a0 / pin configuration space. one 32bit register for up to 128 IRQs / #define AU1300_GPIC_PINCFG 0x1000 #define GPIC_GPIO_TO_BIT(gpio) \ (1 << ((gpio) & 0x1f)) #define GPIC_GPIO_BANKOFF(gpio) \ (((gpio) >> 5) 4) /* Pin Control bits: who owns the pin, what does it do / #define GPIC_CFG_PC_GPIN 0 #define GPIC_CFG_PC_DEV 1 #define GPIC_CFG_PC_GPOLOW 2 #define GPIC_CFG_PC_GPOHIGH 3 #define GPIC_CFG_PC_MASK 3 / assign pin to MIPS IRQ line / #define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) #define GPIC_CFG_IL_MASK (3 << 2) / pin interrupt type setup / #define GPIC_CFG_IC_OFF (0 << 4) #define GPIC_CFG_IC_LEVEL_LOW (1 << 4) #define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) #define GPIC_CFG_IC_EDGE_FALL (5 << 4) #define GPIC_CFG_IC_EDGE_RISE (6 << 4) #define GPIC_CFG_IC_EDGE_BOTH (7 << 4) #define GPIC_CFG_IC_MASK (7 << 4) / allow interrupt to wake cpu from 'wait' / #define GPIC_CFG_IDLEWAKE (1 << 7) /*********************************************************************/ / Au1000 SDRAM memory controller register offsets / #define AU1000_MEM_SDMODE0 0x0000 #define AU1000_MEM_SDMODE1 0x0004 #define AU1000_MEM_SDMODE2 0x0008 #define AU1000_MEM_SDADDR0 0x000C #define AU1000_MEM_SDADDR1 0x0010 #define AU1000_MEM_SDADDR2 0x0014 #define AU1000_MEM_SDREFCFG 0x0018 #define AU1000_MEM_SDPRECMD 0x001C #define AU1000_MEM_SDAUTOREF 0x0020 #define AU1000_MEM_SDWRMD0 0x0024 #define AU1000_MEM_SDWRMD1 0x0028 #define AU1000_MEM_SDWRMD2 0x002C #define AU1000_MEM_SDSLEEP 0x0030 #define AU1000_MEM_SDSMCKE 0x0034 / MEM_SDMODE register content definitions / #define MEM_SDMODE_F (1 << 22) #define MEM_SDMODE_SR (1 << 21) #define MEM_SDMODE_BS (1 << 20) #define MEM_SDMODE_RS (3 << 18) #define MEM_SDMODE_CS (7 << 15) #define MEM_SDMODE_TRAS (15 << 11) #define MEM_SDMODE_TMRD (3 << 9) #define MEM_SDMODE_TWR (3 << 7) #define MEM_SDMODE_TRP (3 << 5) #define MEM_SDMODE_TRCD (3 << 3) #define MEM_SDMODE_TCL (7 << 0) #define MEM_SDMODE_BS_2Bank (0 << 20) #define MEM_SDMODE_BS_4Bank (1 << 20) #define MEM_SDMODE_RS_11Row (0 << 18) #define MEM_SDMODE_RS_12Row (1 << 18) #define MEM_SDMODE_RS_13Row (2 << 18) #define MEM_SDMODE_RS_N(N) ((N) << 18) #define MEM_SDMODE_CS_7Col (0 << 15) #define MEM_SDMODE_CS_8Col (1 << 15) #define MEM_SDMODE_CS_9Col (2 << 15) #define MEM_SDMODE_CS_10Col (3 << 15) #define MEM_SDMODE_CS_11Col (4 << 15) #define MEM_SDMODE_CS_N(N) ((N) << 15) #define MEM_SDMODE_TRAS_N(N) ((N) << 11) #define MEM_SDMODE_TMRD_N(N) ((N) << 9) #define MEM_SDMODE_TWR_N(N) ((N) << 7) #define MEM_SDMODE_TRP_N(N) ((N) << 5) #define MEM_SDMODE_TRCD_N(N) ((N) << 3) #define MEM_SDMODE_TCL_N(N) ((N) << 0) / MEM_SDADDR register contents definitions / #define MEM_SDADDR_E (1 << 20) #define MEM_SDADDR_CSBA (0x03FF << 10) #define MEM_SDADDR_CSMASK (0x03FF << 0) #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) / MEM_SDREFCFG register content definitions / #define MEM_SDREFCFG_TRC (15 << 28) #define MEM_SDREFCFG_TRPM (3 << 26) #define MEM_SDREFCFG_E (1 << 25) #define MEM_SDREFCFG_RE (0x1ffffff << 0) #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) #define MEM_SDREFCFG_REF_N(N) (N) / Au1550 SDRAM Register Offsets / #define AU1550_MEM_SDMODE0 0x0800 #define AU1550_MEM_SDMODE1 0x0808 #define AU1550_MEM_SDMODE2 0x0810 #define AU1550_MEM_SDADDR0 0x0820 #define AU1550_MEM_SDADDR1 0x0828 #define AU1550_MEM_SDADDR2 0x0830 #define AU1550_MEM_SDCONFIGA 0x0840 #define AU1550_MEM_SDCONFIGB 0x0848 #define AU1550_MEM_SDSTAT 0x0850 #define AU1550_MEM_SDERRADDR 0x0858 #define AU1550_MEM_SDSTRIDE0 0x0860 #define AU1550_MEM_SDSTRIDE1 0x0868 #define AU1550_MEM_SDSTRIDE2 0x0870 #define AU1550_MEM_SDWRMD0 0x0880 #define AU1550_MEM_SDWRMD1 0x0888 #define AU1550_MEM_SDWRMD2 0x0890 #define AU1550_MEM_SDPRECMD 0x08C0 #define AU1550_MEM_SDAUTOREF 0x08C8 #define AU1550_MEM_SDSREF 0x08D0 #define AU1550_MEM_SDSLEEP MEM_SDSREF / Static Bus Controller register offsets / #define AU1000_MEM_STCFG0 0x000 #define AU1000_MEM_STTIME0 0x004 #define AU1000_MEM_STADDR0 0x008 #define AU1000_MEM_STCFG1 0x010 #define AU1000_MEM_STTIME1 0x014 #define AU1000_MEM_STADDR1 0x018 #define AU1000_MEM_STCFG2 0x020 #define AU1000_MEM_STTIME2 0x024 #define AU1000_MEM_STADDR2 0x028 #define AU1000_MEM_STCFG3 0x030 #define AU1000_MEM_STTIME3 0x034 #define AU1000_MEM_STADDR3 0x038 #define AU1000_MEM_STNDCTL 0x100 #define AU1000_MEM_STSTAT 0x104 #define MEM_STNAND_CMD 0x0 #define MEM_STNAND_ADDR 0x4 #define MEM_STNAND_DATA 0x20 / Programmable Counters 0 and 1 / #define AU1000_SYS_CNTRCTRL 0x14 # define SYS_CNTRL_E1S (1 << 23) # define SYS_CNTRL_T1S (1 << 20) # define SYS_CNTRL_M21 (1 << 19) # define SYS_CNTRL_M11 (1 << 18) # define SYS_CNTRL_M01 (1 << 17) # define SYS_CNTRL_C1S (1 << 16) # define SYS_CNTRL_BP (1 << 14) # define SYS_CNTRL_EN1 (1 << 13) # define SYS_CNTRL_BT1 (1 << 12) # define SYS_CNTRL_EN0 (1 << 11) # define SYS_CNTRL_BT0 (1 << 10) # define SYS_CNTRL_E0 (1 << 8) # define SYS_CNTRL_E0S (1 << 7) # define SYS_CNTRL_32S (1 << 5) # define SYS_CNTRL_T0S (1 << 4) # define SYS_CNTRL_M20 (1 << 3) # define SYS_CNTRL_M10 (1 << 2) # define SYS_CNTRL_M00 (1 << 1) # define SYS_CNTRL_C0S (1 << 0) / Programmable Counter 0 Registers / #define AU1000_SYS_TOYTRIM 0x00 #define AU1000_SYS_TOYWRITE 0x04 #define AU1000_SYS_TOYMATCH0 0x08 #define AU1000_SYS_TOYMATCH1 0x0c #define AU1000_SYS_TOYMATCH2 0x10 #define AU1000_SYS_TOYREAD 0x40 / Programmable Counter 1 Registers / #define AU1000_SYS_RTCTRIM 0x44 #define AU1000_SYS_RTCWRITE 0x48 #define AU1000_SYS_RTCMATCH0 0x4c #define AU1000_SYS_RTCMATCH1 0x50 #define AU1000_SYS_RTCMATCH2 0x54 #define AU1000_SYS_RTCREAD 0x58 / GPIO / #define AU1000_SYS_PINFUNC 0x2C # define SYS_PF_USB (1 << 15) / 2nd USB device/host / # define SYS_PF_U3 (1 << 14) / GPIO23/U3TXD / # define SYS_PF_U2 (1 << 13) / GPIO22/U2TXD / # define SYS_PF_U1 (1 << 12) / GPIO21/U1TXD / # define SYS_PF_SRC (1 << 11) / GPIO6/SROMCKE / # define SYS_PF_CK5 (1 << 10) / GPIO3/CLK5 / # define SYS_PF_CK4 (1 << 9) / GPIO2/CLK4 / # define SYS_PF_IRF (1 << 8) / GPIO15/IRFIRSEL / # define SYS_PF_UR3 (1 << 7) / GPIO[14:9]/UART3 / # define SYS_PF_I2D (1 << 6) / GPIO8/I2SDI / # define SYS_PF_I2S (1 << 5) / I2S/GPIO[29:31] / # define SYS_PF_NI2 (1 << 4) / NI2/GPIO[24:28] / # define SYS_PF_U0 (1 << 3) / U0TXD/GPIO20 / # define SYS_PF_RD (1 << 2) / IRTXD/GPIO19 / # define SYS_PF_A97 (1 << 1) / AC97/SSL1 / # define SYS_PF_S0 (1 << 0) / SSI_0/GPIO[16:18] / / Au1100 only / # define SYS_PF_PC (1 << 18) / PCMCIA/GPIO[207:204] / # define SYS_PF_LCD (1 << 17) / extern lcd/GPIO[203:200] / # define SYS_PF_CS (1 << 16) / EXTCLK0/32KHz to gpio2 / # define SYS_PF_EX0 (1 << 9) / GPIO2/clock / / Au1550 only. Redefines lots of pins / # define SYS_PF_PSC2_MASK (7 << 17) # define SYS_PF_PSC2_AC97 0 # define SYS_PF_PSC2_SPI 0 # define SYS_PF_PSC2_I2S (1 << 17) # define SYS_PF_PSC2_SMBUS (3 << 17) # define SYS_PF_PSC2_GPIO (7 << 17) # define SYS_PF_PSC3_MASK (7 << 20) # define SYS_PF_PSC3_AC97 0 # define SYS_PF_PSC3_SPI 0 # define SYS_PF_PSC3_I2S (1 << 20) # define SYS_PF_PSC3_SMBUS (3 << 20) # define SYS_PF_PSC3_GPIO (7 << 20) # define SYS_PF_PSC1_S1 (1 << 1) # define SYS_PF_MUST_BE_SET ((1 << 5) \| (1 << 2)) / Au1200 only / #define SYS_PINFUNC_DMA (1 << 31) #define SYS_PINFUNC_S0A (1 << 30) #define SYS_PINFUNC_S1A (1 << 29) #define SYS_PINFUNC_LP0 (1 << 28) #define SYS_PINFUNC_LP1 (1 << 27) #define SYS_PINFUNC_LD16 (1 << 26) #define SYS_PINFUNC_LD8 (1 << 25) #define SYS_PINFUNC_LD1 (1 << 24) #define SYS_PINFUNC_LD0 (1 << 23) #define SYS_PINFUNC_P1A (3 << 21) #define SYS_PINFUNC_P1B (1 << 20) #define SYS_PINFUNC_FS3 (1 << 19) #define SYS_PINFUNC_P0A (3 << 17) #define SYS_PINFUNC_CS (1 << 16) #define SYS_PINFUNC_CIM (1 << 15) #define SYS_PINFUNC_P1C (1 << 14) #define SYS_PINFUNC_U1T (1 << 12) #define SYS_PINFUNC_U1R (1 << 11) #define SYS_PINFUNC_EX1 (1 << 10) #define SYS_PINFUNC_EX0 (1 << 9) #define SYS_PINFUNC_U0R (1 << 8) #define SYS_PINFUNC_MC (1 << 7) #define SYS_PINFUNC_S0B (1 << 6) #define SYS_PINFUNC_S0C (1 << 5) #define SYS_PINFUNC_P0B (1 << 4) #define SYS_PINFUNC_U0T (1 << 3) #define SYS_PINFUNC_S1B (1 << 2) / Power Management / #define AU1000_SYS_SCRATCH0 0x18 #define AU1000_SYS_SCRATCH1 0x1c #define AU1000_SYS_WAKEMSK 0x34 #define AU1000_SYS_ENDIAN 0x38 #define AU1000_SYS_POWERCTRL 0x3c #define AU1000_SYS_WAKESRC 0x5c #define AU1000_SYS_SLPPWR 0x78 #define AU1000_SYS_SLEEP 0x7c #define SYS_WAKEMSK_D2 (1 << 9) #define SYS_WAKEMSK_M2 (1 << 8) #define SYS_WAKEMSK_GPIO(x) (1 << (x)) / Clock Controller / #define AU1000_SYS_FREQCTRL0 0x20 #define AU1000_SYS_FREQCTRL1 0x24 #define AU1000_SYS_CLKSRC 0x28 #define AU1000_SYS_CPUPLL 0x60 #define AU1000_SYS_AUXPLL 0x64 #define AU1300_SYS_AUXPLL2 0x68 /********************************************************************/ / The PCI chip selects are outside the 32bit space, and since we can't * just program the 36bit addresses into BARs, we have to take a chunk * out of the 32bit space and reserve it for PCI. When these addresses * are ioremap()ed, they'll be fixed up to the real 36bit address before * being passed to the real ioremap function. / #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) / for PCI IO it's simpler because we get to do the ioremap ourselves and then * adjust the device's resources. / #define ALCHEMY_PCI_IOWIN_START 0x00001000 #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF #ifdef CONFIG_PCI #define IOPORT_RESOURCE_START 0x00001000 / skip legacy probing / #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL #else / Don't allow any legacy ports probing / #define IOPORT_RESOURCE_START 0x10000000 #define IOPORT_RESOURCE_END 0xffffffff #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xfffffffffULL #endif / PCI controller block register offsets / #define PCI_REG_CMEM 0x0000 #define PCI_REG_CONFIG 0x0004 #define PCI_REG_B2BMASK_CCH 0x0008 #define PCI_REG_B2BBASE0_VID 0x000C #define PCI_REG_B2BBASE1_SID 0x0010 #define PCI_REG_MWMASK_DEV 0x0014 #define PCI_REG_MWBASE_REV_CCL 0x0018 #define PCI_REG_ERR_ADDR 0x001C #define PCI_REG_SPEC_INTACK 0x0020 #define PCI_REG_ID 0x0100 #define PCI_REG_STATCMD 0x0104 #define PCI_REG_CLASSREV 0x0108 #define PCI_REG_PARAM 0x010C #define PCI_REG_MBAR 0x0110 #define PCI_REG_TIMEOUT 0x0140 / PCI controller block register bits / #define PCI_CMEM_E (1 << 28) / enable cacheable memory / #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) #define PCI_CONFIG_ERD (1 << 27) / pci error during R/W / #define PCI_CONFIG_ET (1 << 26) / error in target mode / #define PCI_CONFIG_EF (1 << 25) / fatal error / #define PCI_CONFIG_EP (1 << 24) / parity error / #define PCI_CONFIG_EM (1 << 23) / multiple errors / #define PCI_CONFIG_BM (1 << 22) / bad master error / #define PCI_CONFIG_PD (1 << 20) / PCI Disable / #define PCI_CONFIG_BME (1 << 19) / Byte Mask Enable for reads / #define PCI_CONFIG_NC (1 << 16) / mark mem access non-coherent / #define PCI_CONFIG_IA (1 << 15) / INTA# enabled (target mode) / #define PCI_CONFIG_IP (1 << 13) / int on PCI_PERR# / #define PCI_CONFIG_IS (1 << 12) / int on PCI_SERR# / #define PCI_CONFIG_IMM (1 << 11) / int on master abort / #define PCI_CONFIG_ITM (1 << 10) / int on target abort (as master) / #define PCI_CONFIG_ITT (1 << 9) / int on target abort (as target) / #define PCI_CONFIG_IPB (1 << 8) / int on PERR# in bus master acc / #define PCI_CONFIG_SIC_NO (0 << 6) / no byte mask changes / #define PCI_CONFIG_SIC_BA_ADR (1 << 6) / on byte/hw acc, invert adr bits / #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) / on halfword acc, swap data / #define PCI_CONFIG_SIC_ALL (3 << 6) / swap data bytes on all accesses / #define PCI_CONFIG_ST (1 << 5) / swap data by target transactions / #define PCI_CONFIG_SM (1 << 4) / swap data from PCI ctl / #define PCI_CONFIG_AEN (1 << 3) / enable internal arbiter / #define PCI_CONFIG_R2H (1 << 2) / REQ2# to hi-prio arbiter / #define PCI_CONFIG_R1H (1 << 1) / REQ1# to hi-prio arbiter / #define PCI_CONFIG_CH (1 << 0) / PCI ctl to hi-prio arbiter / #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) / 16 upper bits of class code / #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) #define PCI_ID_DID(x) (((x) & 0xffff) << 16) #define PCI_ID_VID(x) ((x) & 0xffff) #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) #define PCI_STATCMD_CMD(x) ((x) & 0xffff) #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) #define PCI_CLASSREV_REV(x) ((x) & 0xff) #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) #define PCI_PARAM_CLS(x) ((x) & 0xff) #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) / max retries / #define PCI_TIMEOUT_TO(x) ((x) & 0xff) / target ready timeout / /********************************************************************/ #ifndef _LANGUAGE_ASSEMBLY #include <linux/delay.h> #include <linux/types.h> #include <linux/io.h> #include <linux/irq.h> #include <asm/cpu.h> / helpers to access the SYS_* registers / static inline unsigned long alchemy_rdsys(int regofs) { void __iomem b = (void __iomem )KSEG1ADDR(AU1000_SYS_PHYS_ADDR); return __raw_readl(b + regofs); } static inline void alchemy_wrsys(unsigned long v, int regofs) { void __iomem b = (void __iomem )KSEG1ADDR(AU1000_SYS_PHYS_ADDR); __raw_writel(v, b + regofs); wmb(); / drain writebuffer / } / helpers to access static memctrl registers / static inline unsigned long alchemy_rdsmem(int regofs) { void __iomem b = (void __iomem )KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); return __raw_readl(b + regofs); } static inline void alchemy_wrsmem(unsigned long v, int regofs) { void __iomem b = (void __iomem )KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); __raw_writel(v, b + regofs); wmb(); / drain writebuffer / } / Early Au1000 have a write-only SYS_CPUPLL register. / static inline int au1xxx_cpu_has_pll_wo(void) { switch (read_c0_prid()) { case 0x00030100: / Au1000 DA / case 0x00030201: / Au1000 HA / case 0x00030202: / Au1000 HB / return 1; } return 0; } / does CPU need CONFIG[OD] set to fix tons of errata? / static inline int au1xxx_cpu_needs_config_od(void) { / * c0_config.od (bit 19) was write only (and read as 0) on the * early revisions of Alchemy SOCs. It disables the bus trans- * action overlapping and needs to be set to fix various errata. / switch (read_c0_prid()) { case 0x00030100: / Au1000 DA / case 0x00030201: / Au1000 HA / case 0x00030202: / Au1000 HB / case 0x01030200: / Au1500 AB / / * Au1100/Au1200 errata actually keep silence about this bit, * so we set it just in case for those revisions that require * it to be set according to the (now gone) cpu_table. / case 0x02030200: / Au1100 AB / case 0x02030201: / Au1100 BA / case 0x02030202: / Au1100 BC / case 0x04030201: / Au1200 AC / return 1; } return 0; } #define ALCHEMY_CPU_UNKNOWN -1 #define ALCHEMY_CPU_AU1000 0 #define ALCHEMY_CPU_AU1500 1 #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 #define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { switch (read_c0_prid() & (PRID_OPT_MASK \| PRID_COMP_MASK)) { case 0x00030000: return ALCHEMY_CPU_AU1000; break; case 0x01030000: return ALCHEMY_CPU_AU1500; break; case 0x02030000: return ALCHEMY_CPU_AU1100; break; case 0x03030000: return ALCHEMY_CPU_AU1550; break; case 0x04030000: case 0x05030000: return ALCHEMY_CPU_AU1200; break; case 0x800c0000: return ALCHEMY_CPU_AU1300; break; } return ALCHEMY_CPU_UNKNOWN; } / return number of uarts on a given cputype / static inline int alchemy_get_uarts(int type) { switch (type) { case ALCHEMY_CPU_AU1000: case ALCHEMY_CPU_AU1300: return 4; case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1200: return 2; case ALCHEMY_CPU_AU1100: case ALCHEMY_CPU_AU1550: return 3; } return 0; } / enable an UART block if it isn't already / static inline void alchemy_uart_enable(u32 uart_phys) { void __iomem addr = (void __iomem )KSEG1ADDR(uart_phys); / reset, enable clock, deassert reset / if ((__raw_readl(addr + 0x100) & 3) != 3) { __raw_writel(0, addr + 0x100); wmb(); / drain writebuffer / __raw_writel(1, addr + 0x100); wmb(); / drain writebuffer / } __raw_writel(3, addr + 0x100); wmb(); / drain writebuffer / } static inline void alchemy_uart_disable(u32 uart_phys) { void __iomem addr = (void __iomem )KSEG1ADDR(uart_phys); __raw_writel(0, addr + 0x100); / UART_MOD_CNTRL / wmb(); / drain writebuffer / } static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) { void __iomem base = (void __iomem )KSEG1ADDR(uart_phys); int timeout, i; / check LSR TX_EMPTY bit / timeout = 0xffffff; do { if (__raw_readl(base + 0x1c) & 0x20) break; / slow down / for (i = 10000; i; i--) asm volatile ("nop"); } while (--timeout); __raw_writel(c, base + 0x04); / tx / wmb(); / drain writebuffer / } / return number of ethernet MACs on a given cputype / static inline int alchemy_get_macs(int type) { switch (type) { case ALCHEMY_CPU_AU1000: case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1550: return 2; case ALCHEMY_CPU_AU1100: return 1; } return 0; } / PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c / void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); void alchemy_sleep_au1300(void); void au_sleep(void); / USB: arch/mips/alchemy/common/usb.c / enum alchemy_usb_block { ALCHEMY_USB_OHCI0, ALCHEMY_USB_UDC0, ALCHEMY_USB_EHCI0, ALCHEMY_USB_OTG0, ALCHEMY_USB_OHCI1, }; int alchemy_usb_control(int block, int enable); / PCI controller platform data / struct alchemy_pci_platdata { int (board_map_irq)(const struct pci_dev d, u8 slot, u8 pin); int (board_pci_idsel)(unsigned int devsel, int assert); /* bits to set/clear in PCI_CONFIG register / unsigned long pci_cfg_set; unsigned long pci_cfg_clr; }; / The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's * not used to select FIR/SIR mode on the transceiver but as a GPIO. * Instead a CPLD has to be told about the mode. The driver calls the * set_phy_mode() function in addition to driving the IRFIRSEL pin. / #define AU1000_IRDA_PHY_MODE_OFF 0 #define AU1000_IRDA_PHY_MODE_SIR 1 #define AU1000_IRDA_PHY_MODE_FIR 2 struct au1k_irda_platform_data { void (set_phy_mode)(int mode); }; /* Multifunction pins: Each of these pins can either be assigned to the * GPIO controller or a on-chip peripheral. * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to * assign one of these to either the GPIO controller or the device. / enum au1300_multifunc_pins { / wake-from-str pins 0-3 / AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, / external clock sources for PSCs: 4-5 / AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, / 8bit MMC interface on SD0: 6-9 / AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, AU1300_PIN_SD0DAT7, / aux clk input for freqgen 3: 10 / AU1300_PIN_FG3AUX, / UART1 pins: 11-18 / AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, AU1300_PIN_U1RX, AU1300_PIN_U1TX, / UART0 pins: 19-24 / AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, / UART2: 25-26 / AU1300_PIN_U2RX, AU1300_PIN_U2TX, / UART3: 27-28 / AU1300_PIN_U3RX, AU1300_PIN_U3TX, / LCD controller PWMs, ext pixclock: 29-31 / AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, / SD1 interface: 32-37 / AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, / SD2 interface: 38-43 / AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, / PSC0/1 clocks: 44-45 / AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, / PSCs: 46-49/50-53/54-57/58-61 / AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, AU1300_PIN_PSC0D1, AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, AU1300_PIN_PSC1D1, AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, AU1300_PIN_PSC2D1, AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, AU1300_PIN_PSC3D1, / PCMCIA interface: 62-70 / AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, / camera interface H/V sync inputs: 71-72 / AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, / PSC2/3 clocks: 73-74 / AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, }; / GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c / extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); extern void au1300_set_irq_priority(unsigned int irq, int p); extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); / Au1300 allows to disconnect certain blocks from internal power supply / enum au1300_vss_block { AU1300_VSS_MPE = 0, AU1300_VSS_BSA, AU1300_VSS_GPE, AU1300_VSS_MGP, }; extern void au1300_vss_block_control(int block, int enable); enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, AU1000_UART1_INT, AU1000_UART2_INT, AU1000_UART3_INT, AU1000_SSI0_INT, AU1000_SSI1_INT, AU1000_DMA_INT_BASE, AU1000_TOY_INT = AU1000_FIRST_INT + 14, AU1000_TOY_MATCH0_INT, AU1000_TOY_MATCH1_INT, AU1000_TOY_MATCH2_INT, AU1000_RTC_INT, AU1000_RTC_MATCH0_INT, AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, AU1000_IRDA_TX_INT, AU1000_IRDA_RX_INT, AU1000_USB_DEV_REQ_INT, AU1000_USB_DEV_SUS_INT, AU1000_USB_HOST_INT, AU1000_ACSYNC_INT, AU1000_MAC0_DMA_INT, AU1000_MAC1_DMA_INT, AU1000_I2S_UO_INT, AU1000_AC97C_INT, AU1000_GPIO0_INT, AU1000_GPIO1_INT, AU1000_GPIO2_INT, AU1000_GPIO3_INT, AU1000_GPIO4_INT, AU1000_GPIO5_INT, AU1000_GPIO6_INT, AU1000_GPIO7_INT, AU1000_GPIO8_INT, AU1000_GPIO9_INT, AU1000_GPIO10_INT, AU1000_GPIO11_INT, AU1000_GPIO12_INT, AU1000_GPIO13_INT, AU1000_GPIO14_INT, AU1000_GPIO15_INT, AU1000_GPIO16_INT, AU1000_GPIO17_INT, AU1000_GPIO18_INT, AU1000_GPIO19_INT, AU1000_GPIO20_INT, AU1000_GPIO21_INT, AU1000_GPIO22_INT, AU1000_GPIO23_INT, AU1000_GPIO24_INT, AU1000_GPIO25_INT, AU1000_GPIO26_INT, AU1000_GPIO27_INT, AU1000_GPIO28_INT, AU1000_GPIO29_INT, AU1000_GPIO30_INT, AU1000_GPIO31_INT, }; enum soc_au1100_ints { AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, AU1100_UART0_INT = AU1100_FIRST_INT, AU1100_UART1_INT, AU1100_SD_INT, AU1100_UART3_INT, AU1100_SSI0_INT, AU1100_SSI1_INT, AU1100_DMA_INT_BASE, AU1100_TOY_INT = AU1100_FIRST_INT + 14, AU1100_TOY_MATCH0_INT, AU1100_TOY_MATCH1_INT, AU1100_TOY_MATCH2_INT, AU1100_RTC_INT, AU1100_RTC_MATCH0_INT, AU1100_RTC_MATCH1_INT, AU1100_RTC_MATCH2_INT, AU1100_IRDA_TX_INT, AU1100_IRDA_RX_INT, AU1100_USB_DEV_REQ_INT, AU1100_USB_DEV_SUS_INT, AU1100_USB_HOST_INT, AU1100_ACSYNC_INT, AU1100_MAC0_DMA_INT, AU1100_GPIO208_215_INT, AU1100_LCD_INT, AU1100_AC97C_INT, AU1100_GPIO0_INT, AU1100_GPIO1_INT, AU1100_GPIO2_INT, AU1100_GPIO3_INT, AU1100_GPIO4_INT, AU1100_GPIO5_INT, AU1100_GPIO6_INT, AU1100_GPIO7_INT, AU1100_GPIO8_INT, AU1100_GPIO9_INT, AU1100_GPIO10_INT, AU1100_GPIO11_INT, AU1100_GPIO12_INT, AU1100_GPIO13_INT, AU1100_GPIO14_INT, AU1100_GPIO15_INT, AU1100_GPIO16_INT, AU1100_GPIO17_INT, AU1100_GPIO18_INT, AU1100_GPIO19_INT, AU1100_GPIO20_INT, AU1100_GPIO21_INT, AU1100_GPIO22_INT, AU1100_GPIO23_INT, AU1100_GPIO24_INT, AU1100_GPIO25_INT, AU1100_GPIO26_INT, AU1100_GPIO27_INT, AU1100_GPIO28_INT, AU1100_GPIO29_INT, AU1100_GPIO30_INT, AU1100_GPIO31_INT, }; enum soc_au1500_ints { AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, AU1500_UART0_INT = AU1500_FIRST_INT, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_UART3_INT, AU1500_PCI_INTC, AU1500_PCI_INTD, AU1500_DMA_INT_BASE, AU1500_TOY_INT = AU1500_FIRST_INT + 14, AU1500_TOY_MATCH0_INT, AU1500_TOY_MATCH1_INT, AU1500_TOY_MATCH2_INT, AU1500_RTC_INT, AU1500_RTC_MATCH0_INT, AU1500_RTC_MATCH1_INT, AU1500_RTC_MATCH2_INT, AU1500_PCI_ERR_INT, AU1500_RESERVED_INT, AU1500_USB_DEV_REQ_INT, AU1500_USB_DEV_SUS_INT, AU1500_USB_HOST_INT, AU1500_ACSYNC_INT, AU1500_MAC0_DMA_INT, AU1500_MAC1_DMA_INT, AU1500_AC97C_INT = AU1500_FIRST_INT + 31, AU1500_GPIO0_INT, AU1500_GPIO1_INT, AU1500_GPIO2_INT, AU1500_GPIO3_INT, AU1500_GPIO4_INT, AU1500_GPIO5_INT, AU1500_GPIO6_INT, AU1500_GPIO7_INT, AU1500_GPIO8_INT, AU1500_GPIO9_INT, AU1500_GPIO10_INT, AU1500_GPIO11_INT, AU1500_GPIO12_INT, AU1500_GPIO13_INT, AU1500_GPIO14_INT, AU1500_GPIO15_INT, AU1500_GPIO200_INT, AU1500_GPIO201_INT, AU1500_GPIO202_INT, AU1500_GPIO203_INT, AU1500_GPIO20_INT, AU1500_GPIO204_INT, AU1500_GPIO205_INT, AU1500_GPIO23_INT, AU1500_GPIO24_INT, AU1500_GPIO25_INT, AU1500_GPIO26_INT, AU1500_GPIO27_INT, AU1500_GPIO28_INT, AU1500_GPIO206_INT, AU1500_GPIO207_INT, AU1500_GPIO208_215_INT, }; enum soc_au1550_ints { AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, AU1550_UART0_INT = AU1550_FIRST_INT, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_DDMA_INT, AU1550_CRYPTO_INT, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_RST_INT, AU1550_UART1_INT, AU1550_UART3_INT, AU1550_PSC0_INT, AU1550_PSC1_INT, AU1550_PSC2_INT, AU1550_PSC3_INT, AU1550_TOY_INT, AU1550_TOY_MATCH0_INT, AU1550_TOY_MATCH1_INT, AU1550_TOY_MATCH2_INT, AU1550_RTC_INT, AU1550_RTC_MATCH0_INT, AU1550_RTC_MATCH1_INT, AU1550_RTC_MATCH2_INT, AU1550_NAND_INT = AU1550_FIRST_INT + 23, AU1550_USB_DEV_REQ_INT, AU1550_USB_DEV_SUS_INT, AU1550_USB_HOST_INT, AU1550_MAC0_DMA_INT, AU1550_MAC1_DMA_INT, AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, AU1550_GPIO1_INT, AU1550_GPIO2_INT, AU1550_GPIO3_INT, AU1550_GPIO4_INT, AU1550_GPIO5_INT, AU1550_GPIO6_INT, AU1550_GPIO7_INT, AU1550_GPIO8_INT, AU1550_GPIO9_INT, AU1550_GPIO10_INT, AU1550_GPIO11_INT, AU1550_GPIO12_INT, AU1550_GPIO13_INT, AU1550_GPIO14_INT, AU1550_GPIO15_INT, AU1550_GPIO200_INT, AU1550_GPIO201_205_INT, / Logical or of GPIO201:205 / AU1550_GPIO16_INT, AU1550_GPIO17_INT, AU1550_GPIO20_INT, AU1550_GPIO21_INT, AU1550_GPIO22_INT, AU1550_GPIO23_INT, AU1550_GPIO24_INT, AU1550_GPIO25_INT, AU1550_GPIO26_INT, AU1550_GPIO27_INT, AU1550_GPIO28_INT, AU1550_GPIO206_INT, AU1550_GPIO207_INT, AU1550_GPIO208_215_INT, / Logical or of GPIO208:215 / }; enum soc_au1200_ints { AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, AU1200_UART0_INT = AU1200_FIRST_INT, AU1200_SWT_INT, AU1200_SD_INT, AU1200_DDMA_INT, AU1200_MAE_BE_INT, AU1200_GPIO200_INT, AU1200_GPIO201_INT, AU1200_GPIO202_INT, AU1200_UART1_INT, AU1200_MAE_FE_INT, AU1200_PSC0_INT, AU1200_PSC1_INT, AU1200_AES_INT, AU1200_CAMERA_INT, AU1200_TOY_INT, AU1200_TOY_MATCH0_INT, AU1200_TOY_MATCH1_INT, AU1200_TOY_MATCH2_INT, AU1200_RTC_INT, AU1200_RTC_MATCH0_INT, AU1200_RTC_MATCH1_INT, AU1200_RTC_MATCH2_INT, AU1200_GPIO203_INT, AU1200_NAND_INT, AU1200_GPIO204_INT, AU1200_GPIO205_INT, AU1200_GPIO206_INT, AU1200_GPIO207_INT, AU1200_GPIO208_215_INT, / Logical OR of 208:215 / AU1200_USB_INT, AU1200_LCD_INT, AU1200_MAE_BOTH_INT, AU1200_GPIO0_INT, AU1200_GPIO1_INT, AU1200_GPIO2_INT, AU1200_GPIO3_INT, AU1200_GPIO4_INT, AU1200_GPIO5_INT, AU1200_GPIO6_INT, AU1200_GPIO7_INT, AU1200_GPIO8_INT, AU1200_GPIO9_INT, AU1200_GPIO10_INT, AU1200_GPIO11_INT, AU1200_GPIO12_INT, AU1200_GPIO13_INT, AU1200_GPIO14_INT, AU1200_GPIO15_INT, AU1200_GPIO16_INT, AU1200_GPIO17_INT, AU1200_GPIO18_INT, AU1200_GPIO19_INT, AU1200_GPIO20_INT, AU1200_GPIO21_INT, AU1200_GPIO22_INT, AU1200_GPIO23_INT, AU1200_GPIO24_INT, AU1200_GPIO25_INT, AU1200_GPIO26_INT, AU1200_GPIO27_INT, AU1200_GPIO28_INT, AU1200_GPIO29_INT, AU1200_GPIO30_INT, AU1200_GPIO31_INT, }; #endif / !defined (_LANGUAGE_ASSEMBLY) / #endif PK��5^�ZmƏI/��/��prom.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __AU1X00_PROM_H #define __AU1X00_PROM_H extern int prom_argc; extern char prom_argv; extern char prom_envp; extern void prom_init_cmdline(void); extern char prom_getenv(char envname); extern int prom_get_ethernet_addr(char ethernet_addr); #endif PK��5^�Z��?�K9��K9��au1xxx_psc.hnu��[��/* * * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * * Copyright 2004 Embedded Edge, LLC * dan@embeddededge.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. / / Specifics for the Au1xxx Programmable Serial Controllers, first * seen in the AU1550 part. / #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ / * The PSC select and control registers are common to all protocols. / #define PSC_SEL_OFFSET 0x00000000 #define PSC_CTRL_OFFSET 0x00000004 #define PSC_SEL_CLK_MASK (3 << 4) #define PSC_SEL_CLK_INTCLK (0 << 4) #define PSC_SEL_CLK_EXTCLK (1 << 4) #define PSC_SEL_CLK_SERCLK (2 << 4) #define PSC_SEL_PS_MASK 0x00000007 #define PSC_SEL_PS_DISABLED 0 #define PSC_SEL_PS_SPIMODE 2 #define PSC_SEL_PS_I2SMODE 3 #define PSC_SEL_PS_AC97MODE 4 #define PSC_SEL_PS_SMBUSMODE 5 #define PSC_CTRL_DISABLE 0 #define PSC_CTRL_SUSPEND 2 #define PSC_CTRL_ENABLE 3 / AC97 Registers. / #define PSC_AC97CFG_OFFSET 0x00000008 #define PSC_AC97MSK_OFFSET 0x0000000c #define PSC_AC97PCR_OFFSET 0x00000010 #define PSC_AC97STAT_OFFSET 0x00000014 #define PSC_AC97EVNT_OFFSET 0x00000018 #define PSC_AC97TXRX_OFFSET 0x0000001c #define PSC_AC97CDC_OFFSET 0x00000020 #define PSC_AC97RST_OFFSET 0x00000024 #define PSC_AC97GPO_OFFSET 0x00000028 #define PSC_AC97GPI_OFFSET 0x0000002c / AC97 Config Register. / #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) #define PSC_AC97CFG_RT_FIFO2 (1 << 30) #define PSC_AC97CFG_RT_FIFO4 (2 << 30) #define PSC_AC97CFG_RT_FIFO8 (3 << 30) #define PSC_AC97CFG_TT_MASK (3 << 28) #define PSC_AC97CFG_TT_FIFO1 (0 << 28) #define PSC_AC97CFG_TT_FIFO2 (1 << 28) #define PSC_AC97CFG_TT_FIFO4 (2 << 28) #define PSC_AC97CFG_TT_FIFO8 (3 << 28) #define PSC_AC97CFG_DD_DISABLE (1 << 27) #define PSC_AC97CFG_DE_ENABLE (1 << 26) #define PSC_AC97CFG_SE_ENABLE (1 << 25) #define PSC_AC97CFG_LEN_MASK (0xf << 21) #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) #define PSC_AC97CFG_GE_ENABLE (1) / Enable slots 3-12. / #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) / * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the * arithmetic in the macro. / #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) 2) + 2) /* AC97 Mask Register. / #define PSC_AC97MSK_GR (1 << 25) #define PSC_AC97MSK_CD (1 << 24) #define PSC_AC97MSK_RR (1 << 13) #define PSC_AC97MSK_RO (1 << 12) #define PSC_AC97MSK_RU (1 << 11) #define PSC_AC97MSK_TR (1 << 10) #define PSC_AC97MSK_TO (1 << 9) #define PSC_AC97MSK_TU (1 << 8) #define PSC_AC97MSK_RD (1 << 5) #define PSC_AC97MSK_TD (1 << 4) #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR \| PSC_AC97MSK_CD \| \ PSC_AC97MSK_RR \| PSC_AC97MSK_RO \| \ PSC_AC97MSK_RU \| PSC_AC97MSK_TR \| \ PSC_AC97MSK_TO \| PSC_AC97MSK_TU \| \ PSC_AC97MSK_RD \| PSC_AC97MSK_TD) / AC97 Protocol Control Register. / #define PSC_AC97PCR_RC (1 << 6) #define PSC_AC97PCR_RP (1 << 5) #define PSC_AC97PCR_RS (1 << 4) #define PSC_AC97PCR_TC (1 << 2) #define PSC_AC97PCR_TP (1 << 1) #define PSC_AC97PCR_TS (1 << 0) / AC97 Status register (read only). / #define PSC_AC97STAT_CB (1 << 26) #define PSC_AC97STAT_CP (1 << 25) #define PSC_AC97STAT_CR (1 << 24) #define PSC_AC97STAT_RF (1 << 13) #define PSC_AC97STAT_RE (1 << 12) #define PSC_AC97STAT_RR (1 << 11) #define PSC_AC97STAT_TF (1 << 10) #define PSC_AC97STAT_TE (1 << 9) #define PSC_AC97STAT_TR (1 << 8) #define PSC_AC97STAT_RB (1 << 5) #define PSC_AC97STAT_TB (1 << 4) #define PSC_AC97STAT_DI (1 << 2) #define PSC_AC97STAT_DR (1 << 1) #define PSC_AC97STAT_SR (1 << 0) / AC97 Event Register. / #define PSC_AC97EVNT_GR (1 << 25) #define PSC_AC97EVNT_CD (1 << 24) #define PSC_AC97EVNT_RR (1 << 13) #define PSC_AC97EVNT_RO (1 << 12) #define PSC_AC97EVNT_RU (1 << 11) #define PSC_AC97EVNT_TR (1 << 10) #define PSC_AC97EVNT_TO (1 << 9) #define PSC_AC97EVNT_TU (1 << 8) #define PSC_AC97EVNT_RD (1 << 5) #define PSC_AC97EVNT_TD (1 << 4) / CODEC Command Register. / #define PSC_AC97CDC_RD (1 << 25) #define PSC_AC97CDC_ID_MASK (3 << 23) #define PSC_AC97CDC_INDX_MASK (0x7f << 16) #define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) / AC97 Reset Control Register. / #define PSC_AC97RST_RST (1 << 1) #define PSC_AC97RST_SNC (1 << 0) / PSC in I2S Mode. / typedef struct psc_i2s { u32 psc_sel; u32 psc_ctrl; u32 psc_i2scfg; u32 psc_i2smsk; u32 psc_i2spcr; u32 psc_i2sstat; u32 psc_i2sevent; u32 psc_i2stxrx; u32 psc_i2sudf; } psc_i2s_t; #define PSC_I2SCFG_OFFSET 0x08 #define PSC_I2SMASK_OFFSET 0x0C #define PSC_I2SPCR_OFFSET 0x10 #define PSC_I2SSTAT_OFFSET 0x14 #define PSC_I2SEVENT_OFFSET 0x18 #define PSC_I2SRXTX_OFFSET 0x1C #define PSC_I2SUDF_OFFSET 0x20 / I2S Config Register. / #define PSC_I2SCFG_RT_MASK (3 << 30) #define PSC_I2SCFG_RT_FIFO1 (0 << 30) #define PSC_I2SCFG_RT_FIFO2 (1 << 30) #define PSC_I2SCFG_RT_FIFO4 (2 << 30) #define PSC_I2SCFG_RT_FIFO8 (3 << 30) #define PSC_I2SCFG_TT_MASK (3 << 28) #define PSC_I2SCFG_TT_FIFO1 (0 << 28) #define PSC_I2SCFG_TT_FIFO2 (1 << 28) #define PSC_I2SCFG_TT_FIFO4 (2 << 28) #define PSC_I2SCFG_TT_FIFO8 (3 << 28) #define PSC_I2SCFG_DD_DISABLE (1 << 27) #define PSC_I2SCFG_DE_ENABLE (1 << 26) #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) #define PSC_I2SCFG_WI (1 << 15) #define PSC_I2SCFG_DIV_MASK (3 << 13) #define PSC_I2SCFG_DIV2 (0 << 13) #define PSC_I2SCFG_DIV4 (1 << 13) #define PSC_I2SCFG_DIV8 (2 << 13) #define PSC_I2SCFG_DIV16 (3 << 13) #define PSC_I2SCFG_BI (1 << 12) #define PSC_I2SCFG_BUF (1 << 11) #define PSC_I2SCFG_MLJ (1 << 10) #define PSC_I2SCFG_XM (1 << 9) / The word length equation is simply LEN+1. / #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) #define PSC_I2SCFG_LB (1 << 2) #define PSC_I2SCFG_MLF (1 << 1) #define PSC_I2SCFG_MS (1 << 0) / I2S Mask Register. / #define PSC_I2SMSK_RR (1 << 13) #define PSC_I2SMSK_RO (1 << 12) #define PSC_I2SMSK_RU (1 << 11) #define PSC_I2SMSK_TR (1 << 10) #define PSC_I2SMSK_TO (1 << 9) #define PSC_I2SMSK_TU (1 << 8) #define PSC_I2SMSK_RD (1 << 5) #define PSC_I2SMSK_TD (1 << 4) #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR \| PSC_I2SMSK_RO \| \ PSC_I2SMSK_RU \| PSC_I2SMSK_TR \| \ PSC_I2SMSK_TO \| PSC_I2SMSK_TU \| \ PSC_I2SMSK_RD \| PSC_I2SMSK_TD) / I2S Protocol Control Register. / #define PSC_I2SPCR_RC (1 << 6) #define PSC_I2SPCR_RP (1 << 5) #define PSC_I2SPCR_RS (1 << 4) #define PSC_I2SPCR_TC (1 << 2) #define PSC_I2SPCR_TP (1 << 1) #define PSC_I2SPCR_TS (1 << 0) / I2S Status register (read only). / #define PSC_I2SSTAT_RF (1 << 13) #define PSC_I2SSTAT_RE (1 << 12) #define PSC_I2SSTAT_RR (1 << 11) #define PSC_I2SSTAT_TF (1 << 10) #define PSC_I2SSTAT_TE (1 << 9) #define PSC_I2SSTAT_TR (1 << 8) #define PSC_I2SSTAT_RB (1 << 5) #define PSC_I2SSTAT_TB (1 << 4) #define PSC_I2SSTAT_DI (1 << 2) #define PSC_I2SSTAT_DR (1 << 1) #define PSC_I2SSTAT_SR (1 << 0) / I2S Event Register. / #define PSC_I2SEVNT_RR (1 << 13) #define PSC_I2SEVNT_RO (1 << 12) #define PSC_I2SEVNT_RU (1 << 11) #define PSC_I2SEVNT_TR (1 << 10) #define PSC_I2SEVNT_TO (1 << 9) #define PSC_I2SEVNT_TU (1 << 8) #define PSC_I2SEVNT_RD (1 << 5) #define PSC_I2SEVNT_TD (1 << 4) / PSC in SPI Mode. / typedef struct psc_spi { u32 psc_sel; u32 psc_ctrl; u32 psc_spicfg; u32 psc_spimsk; u32 psc_spipcr; u32 psc_spistat; u32 psc_spievent; u32 psc_spitxrx; } psc_spi_t; / SPI Config Register. / #define PSC_SPICFG_RT_MASK (3 << 30) #define PSC_SPICFG_RT_FIFO1 (0 << 30) #define PSC_SPICFG_RT_FIFO2 (1 << 30) #define PSC_SPICFG_RT_FIFO4 (2 << 30) #define PSC_SPICFG_RT_FIFO8 (3 << 30) #define PSC_SPICFG_TT_MASK (3 << 28) #define PSC_SPICFG_TT_FIFO1 (0 << 28) #define PSC_SPICFG_TT_FIFO2 (1 << 28) #define PSC_SPICFG_TT_FIFO4 (2 << 28) #define PSC_SPICFG_TT_FIFO8 (3 << 28) #define PSC_SPICFG_DD_DISABLE (1 << 27) #define PSC_SPICFG_DE_ENABLE (1 << 26) #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) #define PSC_SPICFG_DIV2 0 #define PSC_SPICFG_DIV4 1 #define PSC_SPICFG_DIV8 2 #define PSC_SPICFG_DIV16 3 #define PSC_SPICFG_BI (1 << 12) #define PSC_SPICFG_PSE (1 << 11) #define PSC_SPICFG_CGE (1 << 10) #define PSC_SPICFG_CDE (1 << 9) #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) #define PSC_SPICFG_LB (1 << 3) #define PSC_SPICFG_MLF (1 << 1) #define PSC_SPICFG_MO (1 << 0) / SPI Mask Register. / #define PSC_SPIMSK_MM (1 << 16) #define PSC_SPIMSK_RR (1 << 13) #define PSC_SPIMSK_RO (1 << 12) #define PSC_SPIMSK_RU (1 << 11) #define PSC_SPIMSK_TR (1 << 10) #define PSC_SPIMSK_TO (1 << 9) #define PSC_SPIMSK_TU (1 << 8) #define PSC_SPIMSK_SD (1 << 5) #define PSC_SPIMSK_MD (1 << 4) #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM \| PSC_SPIMSK_RR \| \ PSC_SPIMSK_RO \| PSC_SPIMSK_TO \| \ PSC_SPIMSK_TU \| PSC_SPIMSK_SD \| \ PSC_SPIMSK_MD) / SPI Protocol Control Register. / #define PSC_SPIPCR_RC (1 << 6) #define PSC_SPIPCR_SP (1 << 5) #define PSC_SPIPCR_SS (1 << 4) #define PSC_SPIPCR_TC (1 << 2) #define PSC_SPIPCR_MS (1 << 0) / SPI Status register (read only). / #define PSC_SPISTAT_RF (1 << 13) #define PSC_SPISTAT_RE (1 << 12) #define PSC_SPISTAT_RR (1 << 11) #define PSC_SPISTAT_TF (1 << 10) #define PSC_SPISTAT_TE (1 << 9) #define PSC_SPISTAT_TR (1 << 8) #define PSC_SPISTAT_SB (1 << 5) #define PSC_SPISTAT_MB (1 << 4) #define PSC_SPISTAT_DI (1 << 2) #define PSC_SPISTAT_DR (1 << 1) #define PSC_SPISTAT_SR (1 << 0) / SPI Event Register. / #define PSC_SPIEVNT_MM (1 << 16) #define PSC_SPIEVNT_RR (1 << 13) #define PSC_SPIEVNT_RO (1 << 12) #define PSC_SPIEVNT_RU (1 << 11) #define PSC_SPIEVNT_TR (1 << 10) #define PSC_SPIEVNT_TO (1 << 9) #define PSC_SPIEVNT_TU (1 << 8) #define PSC_SPIEVNT_SD (1 << 5) #define PSC_SPIEVNT_MD (1 << 4) / Transmit register control. / #define PSC_SPITXRX_LC (1 << 29) #define PSC_SPITXRX_SR (1 << 28) / SMBus Config Register. / #define PSC_SMBCFG_RT_MASK (3 << 30) #define PSC_SMBCFG_RT_FIFO1 (0 << 30) #define PSC_SMBCFG_RT_FIFO2 (1 << 30) #define PSC_SMBCFG_RT_FIFO4 (2 << 30) #define PSC_SMBCFG_RT_FIFO8 (3 << 30) #define PSC_SMBCFG_TT_MASK (3 << 28) #define PSC_SMBCFG_TT_FIFO1 (0 << 28) #define PSC_SMBCFG_TT_FIFO2 (1 << 28) #define PSC_SMBCFG_TT_FIFO4 (2 << 28) #define PSC_SMBCFG_TT_FIFO8 (3 << 28) #define PSC_SMBCFG_DD_DISABLE (1 << 27) #define PSC_SMBCFG_DE_ENABLE (1 << 26) #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) #define PSC_SMBCFG_DIV2 0 #define PSC_SMBCFG_DIV4 1 #define PSC_SMBCFG_DIV8 2 #define PSC_SMBCFG_DIV16 3 #define PSC_SMBCFG_GCE (1 << 9) #define PSC_SMBCFG_SFM (1 << 8) #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) / SMBus Mask Register. / #define PSC_SMBMSK_DN (1 << 30) #define PSC_SMBMSK_AN (1 << 29) #define PSC_SMBMSK_AL (1 << 28) #define PSC_SMBMSK_RR (1 << 13) #define PSC_SMBMSK_RO (1 << 12) #define PSC_SMBMSK_RU (1 << 11) #define PSC_SMBMSK_TR (1 << 10) #define PSC_SMBMSK_TO (1 << 9) #define PSC_SMBMSK_TU (1 << 8) #define PSC_SMBMSK_SD (1 << 5) #define PSC_SMBMSK_MD (1 << 4) #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN \| PSC_SMBMSK_AN \| \ PSC_SMBMSK_AL \| PSC_SMBMSK_RR \| \ PSC_SMBMSK_RO \| PSC_SMBMSK_TO \| \ PSC_SMBMSK_TU \| PSC_SMBMSK_SD \| \ PSC_SMBMSK_MD) / SMBus Protocol Control Register. / #define PSC_SMBPCR_DC (1 << 2) #define PSC_SMBPCR_MS (1 << 0) / SMBus Status register (read only). / #define PSC_SMBSTAT_BB (1 << 28) #define PSC_SMBSTAT_RF (1 << 13) #define PSC_SMBSTAT_RE (1 << 12) #define PSC_SMBSTAT_RR (1 << 11) #define PSC_SMBSTAT_TF (1 << 10) #define PSC_SMBSTAT_TE (1 << 9) #define PSC_SMBSTAT_TR (1 << 8) #define PSC_SMBSTAT_SB (1 << 5) #define PSC_SMBSTAT_MB (1 << 4) #define PSC_SMBSTAT_DI (1 << 2) #define PSC_SMBSTAT_DR (1 << 1) #define PSC_SMBSTAT_SR (1 << 0) / SMBus Event Register. / #define PSC_SMBEVNT_DN (1 << 30) #define PSC_SMBEVNT_AN (1 << 29) #define PSC_SMBEVNT_AL (1 << 28) #define PSC_SMBEVNT_RR (1 << 13) #define PSC_SMBEVNT_RO (1 << 12) #define PSC_SMBEVNT_RU (1 << 11) #define PSC_SMBEVNT_TR (1 << 10) #define PSC_SMBEVNT_TO (1 << 9) #define PSC_SMBEVNT_TU (1 << 8) #define PSC_SMBEVNT_SD (1 << 5) #define PSC_SMBEVNT_MD (1 << 4) #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN \| PSC_SMBEVNT_AN \| \ PSC_SMBEVNT_AL \| PSC_SMBEVNT_RR \| \ PSC_SMBEVNT_RO \| PSC_SMBEVNT_TO \| \ PSC_SMBEVNT_TU \| PSC_SMBEVNT_SD \| \ PSC_SMBEVNT_MD) / Transmit register control. / #define PSC_SMBTXRX_RSR (1 << 28) #define PSC_SMBTXRX_STP (1 << 29) #define PSC_SMBTXRX_DATAMASK 0xff / SMBus protocol timers register. / #define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) #endif / _AU1000_PSC_H_ / PK��5^�Z�Shy��au1xxx_eth.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __AU1X00_ETH_DATA_H #define __AU1X00_ETH_DATA_H / Platform specific PHY configuration passed to the MAC driver / struct au1000_eth_platform_data { int phy_static_config; int phy_search_highest_addr; int phy1_search_mac0; int phy_addr; int phy_busid; int phy_irq; char mac[6]; }; void __init au1xxx_override_eth_cfg(unsigned port, struct au1000_eth_platform_data eth_data); #endif /* __AU1X00_ETH_DATA_H / PK��5^�ZU�� au1200fb.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * platform data for au1200fb driver. / #ifndef _AU1200FB_PLAT_H_ #define _AU1200FB_PLAT_H_ struct au1200fb_platdata { int (panel_index)(void); int (panel_init)(void); int (panel_shutdown)(void); }; #endif PK��5^�Zm<� �� cpu-feature-overrides.hnu��[��/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. / #ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H #define cpu_has_tlb 1 #define cpu_has_ftlb 0 #define cpu_has_tlbinv 0 #define cpu_has_segments 0 #define cpu_has_eva 0 #define cpu_has_htw 0 #define cpu_has_ldpte 0 #define cpu_has_rixiex 0 #define cpu_has_maar 0 #define cpu_has_rw_llb 0 #define cpu_has_3kex 0 #define cpu_has_4kex 1 #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_tx39_cache 0 #define cpu_has_fpu 0 #define cpu_has_32fpr 0 #define cpu_has_counter 1 #define cpu_has_watch 1 #define cpu_has_divec 1 #define cpu_has_vce 0 #define cpu_has_cache_cdex_p 0 #define cpu_has_cache_cdex_s 0 #define cpu_has_prefetch 1 #define cpu_has_mcheck 1 #define cpu_has_ejtag 1 #define cpu_has_llsc 1 #define cpu_has_guestctl0ext 0 #define cpu_has_guestctl1 0 #define cpu_has_guestctl2 0 #define cpu_has_guestid 0 #define cpu_has_drg 0 #define cpu_has_mips16 0 #define cpu_has_mips16e2 0 #define cpu_has_mdmx 0 #define cpu_has_mips3d 0 #define cpu_has_smartmips 0 #define cpu_has_rixi 0 #define cpu_has_mmips 0 #define cpu_has_lpa 0 #define cpu_has_mhv 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 1 #define cpu_has_pindexed_dcache 0 #define cpu_has_mips32r1 1 #define cpu_has_mips32r2 0 #define cpu_has_mips32r6 0 #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 0 #define cpu_has_mips64r6 0 #define cpu_has_dsp 0 #define cpu_has_dsp2 0 #define cpu_has_dsp3 0 #define cpu_has_mipsmt 0 #define cpu_has_vp 0 #define cpu_has_userlocal 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 0 #define cpu_tcache_line_size() 0 #define cpu_has_perf_cntr_intr_bit 0 #define cpu_has_vz 0 #define cpu_has_msa 0 #define cpu_has_ufr 0 #define cpu_has_fre 0 #define cpu_has_cdmm 0 #define cpu_has_small_pages 0 #define cpu_has_nan_legacy 1 #define cpu_has_nan_2008 1 #define cpu_has_ebase_wg 0 #define cpu_has_badinstr 0 #define cpu_has_badinstrp 0 #define cpu_has_contextconfig 0 #define cpu_has_perf 0 #endif / __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H / PK��5^�Z�sߏ�+��+��au1000_dma.hnu��[��/ * BRIEF MODULE DESCRIPTION * Defines for using and allocating DMA channels on the Alchemy * Au1x00 MIPS processors. * * Copyright 2000, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. <source@mvista.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. * / #ifndef __ASM_AU1000_DMA_H #define __ASM_AU1000_DMA_H #include <linux/io.h> / need byte IO / #include <linux/spinlock.h> / And spinlocks / #include <linux/delay.h> #define NUM_AU1000_DMA_CHANNELS 8 / DMA Channel Register Offsets / #define DMA_MODE_SET 0x00000000 #define DMA_MODE_READ DMA_MODE_SET #define DMA_MODE_CLEAR 0x00000004 / DMA Mode register bits follow / #define DMA_DAH_MASK (0x0f << 20) #define DMA_DID_BIT 16 #define DMA_DID_MASK (0x0f << DMA_DID_BIT) #define DMA_DS (1 << 15) #define DMA_BE (1 << 13) #define DMA_DR (1 << 12) #define DMA_TS8 (1 << 11) #define DMA_DW_BIT 9 #define DMA_DW_MASK (0x03 << DMA_DW_BIT) #define DMA_DW8 (0 << DMA_DW_BIT) #define DMA_DW16 (1 << DMA_DW_BIT) #define DMA_DW32 (2 << DMA_DW_BIT) #define DMA_NC (1 << 8) #define DMA_IE (1 << 7) #define DMA_HALT (1 << 6) #define DMA_GO (1 << 5) #define DMA_AB (1 << 4) #define DMA_D1 (1 << 3) #define DMA_BE1 (1 << 2) #define DMA_D0 (1 << 1) #define DMA_BE0 (1 << 0) #define DMA_PERIPHERAL_ADDR 0x00000008 #define DMA_BUFFER0_START 0x0000000C #define DMA_BUFFER1_START 0x00000014 #define DMA_BUFFER0_COUNT 0x00000010 #define DMA_BUFFER1_COUNT 0x00000018 #define DMA_BAH_BIT 16 #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT) #define DMA_COUNT_BIT 0 #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT) / DMA Device IDs follow / enum { DMA_ID_UART0_TX = 0, DMA_ID_UART0_RX, DMA_ID_GP04, DMA_ID_GP05, DMA_ID_AC97C_TX, DMA_ID_AC97C_RX, DMA_ID_UART3_TX, DMA_ID_UART3_RX, DMA_ID_USBDEV_EP0_RX, DMA_ID_USBDEV_EP0_TX, DMA_ID_USBDEV_EP2_TX, DMA_ID_USBDEV_EP3_TX, DMA_ID_USBDEV_EP4_RX, DMA_ID_USBDEV_EP5_RX, DMA_ID_I2S_TX, DMA_ID_I2S_RX, DMA_NUM_DEV }; / DMA Device ID's for 2nd bank (AU1100) follow / enum { DMA_ID_SD0_TX = 0, DMA_ID_SD0_RX, DMA_ID_SD1_TX, DMA_ID_SD1_RX, DMA_NUM_DEV_BANK2 }; struct dma_chan { int dev_id; / this channel is allocated if >= 0, / / free otherwise / void __iomem io; const char dev_str; int irq; void irq_dev; unsigned int fifo_addr; unsigned int mode; }; /* These are in arch/mips/au1000/common/dma.c / extern struct dma_chan au1000_dma_table[]; extern int request_au1000_dma(int dev_id, const char dev_str, irq_handler_t irqhandler, unsigned long irqflags, void irq_dev_id); extern void free_au1000_dma(unsigned int dmanr); extern int au1000_dma_read_proc(char buf, char *start, off_t fpos, int length, int eof, void data); extern void dump_au1000_dma_channel(unsigned int dmanr); extern spinlock_t au1000_dma_spin_lock; static inline struct dma_chan get_dma_chan(unsigned int dmanr) { if (dmanr >= NUM_AU1000_DMA_CHANNELS \|\| au1000_dma_table[dmanr].dev_id < 0) return NULL; return &au1000_dma_table[dmanr]; } static inline unsigned long claim_dma_lock(void) { unsigned long flags; spin_lock_irqsave(&au1000_dma_spin_lock, flags); return flags; } static inline void release_dma_lock(unsigned long flags) { spin_unlock_irqrestore(&au1000_dma_spin_lock, flags); } /* * Set the DMA buffer enable bits in the mode register. / static inline void enable_dma_buffer0(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); } static inline void enable_dma_buffer1(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); } static inline void enable_dma_buffers(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_BE0 \| DMA_BE1, chan->io + DMA_MODE_SET); } static inline void start_dma(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); } #define DMA_HALT_POLL 0x5000 static inline void halt_dma(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); int i; if (!chan) return; __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); /* Poll the halt bit / for (i = 0; i < DMA_HALT_POLL; i++) if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) break; if (i == DMA_HALT_POLL) printk(KERN_INFO "halt_dma: HALT poll expired!\n"); } static inline void disable_dma(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; halt_dma(dmanr); /* Now we can disable the buffers / __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); } static inline int dma_halted(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return 1; return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; } /* Initialize a DMA channel. / static inline void init_dma(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); u32 mode; if (!chan) return; disable_dma(dmanr); /* Set device FIFO address / __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); mode = chan->mode \| (chan->dev_id << DMA_DID_BIT); if (chan->irq) mode \|= DMA_IE; __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); __raw_writel(mode, chan->io + DMA_MODE_SET); } / * Set mode for a specific DMA channel / static inline void set_dma_mode(unsigned int dmanr, unsigned int mode) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; /* * set_dma_mode is only allowed to change endianess, direction, * transfer size, device FIFO width, and coherency settings. * Make sure anything else is masked off. / mode &= (DMA_BE \| DMA_DR \| DMA_TS8 \| DMA_DW_MASK \| DMA_NC); chan->mode &= ~(DMA_BE \| DMA_DR \| DMA_TS8 \| DMA_DW_MASK \| DMA_NC); chan->mode \|= mode; } static inline unsigned int get_dma_mode(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return 0; return chan->mode; } static inline int get_dma_active_buffer(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return -1; return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; } / * Set the device FIFO address for a specific DMA channel - only * applicable to GPO4 and GPO5. All the other devices have fixed * FIFO addresses. / static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; if (chan->mode & DMA_DS) /* second bank of device IDs / return; if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) return; __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); } / * Clear the DMA buffer done bits in the mode register. / static inline void clear_dma_done0(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); } static inline void clear_dma_done1(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); } / * This does nothing - not applicable to Au1000 DMA. / static inline void set_dma_page(unsigned int dmanr, char pagenr) { } / * Set Buffer 0 transfer address for specific DMA channel. / static inline void set_dma_addr0(unsigned int dmanr, unsigned int a) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(a, chan->io + DMA_BUFFER0_START); } /* * Set Buffer 1 transfer address for specific DMA channel. / static inline void set_dma_addr1(unsigned int dmanr, unsigned int a) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; __raw_writel(a, chan->io + DMA_BUFFER1_START); } /* * Set Buffer 0 transfer size (max 64k) for a specific DMA channel. / static inline void set_dma_count0(unsigned int dmanr, unsigned int count) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; count &= DMA_COUNT_MASK; __raw_writel(count, chan->io + DMA_BUFFER0_COUNT); } /* * Set Buffer 1 transfer size (max 64k) for a specific DMA channel. / static inline void set_dma_count1(unsigned int dmanr, unsigned int count) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; count &= DMA_COUNT_MASK; __raw_writel(count, chan->io + DMA_BUFFER1_COUNT); } /* * Set both buffer transfer sizes (max 64k) for a specific DMA channel. / static inline void set_dma_count(unsigned int dmanr, unsigned int count) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return; count &= DMA_COUNT_MASK; __raw_writel(count, chan->io + DMA_BUFFER0_COUNT); __raw_writel(count, chan->io + DMA_BUFFER1_COUNT); } /* * Returns which buffer has its done bit set in the mode register. * Returns -1 if neither or both done bits set. / static inline unsigned int get_dma_buffer_done(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return 0; return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 \| DMA_D1); } /* * Returns the DMA channel's Buffer Done IRQ number. / static inline int get_dma_done_irq(unsigned int dmanr) { struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return -1; return chan->irq; } /* * Get DMA residue count. Returns the number of _bytes_ left to transfer. / static inline int get_dma_residue(unsigned int dmanr) { int curBufCntReg, count; struct dma_chan chan = get_dma_chan(dmanr); if (!chan) return 0; curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT; count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; if ((chan->mode & DMA_DW_MASK) == DMA_DW16) count <<= 1; else if ((chan->mode & DMA_DW_MASK) == DMA_DW32) count <<= 2; return count; } #endif /* __ASM_AU1000_DMA_H */ PK��5^�Z k�4r ��r �� gpio-au1300.hnu��[��PK��5^�ZW 2�� au1550_spi.hnu��[��PK��5^�Z�/�E�4��4��au1xxx_dbdma.hnu��[��PK��5^�Z�}td��d��A��au1100_mmc.hnu��[��PK��5^�Z��I4��4�� Y��au1550nd.hnu��[��PK��5^�Z��a]c6��c6�� [��gpio-au1000.hnu��[��PK��5^�Z_��5��5��au1000.hnu��[��PK��5^�ZmƏI/��/��(�prom.hnu��[��PK��5^�Z��?�K9��K9��})�au1xxx_psc.hnu��[��PK��5^�Z�Shy��c�au1xxx_eth.hnu��[��PK��5^�ZU�� e�au1200fb.hnu��[��PK��5^�Zm<� �� Rf�cpu-feature-overrides.hnu��[��PK��5^�Z�sߏ�+��+��p�au1000_dma.hnu��[��PK��

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