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PK��k��Z�V��cs5536/cs5536.hnu��[��/* SPDX-License-Identifier: GPL-2.0 / / * The header file of cs5536 south bridge. * * Copyright (C) 2007 Lemote, Inc. * Author : jlliu <liujl@lemote.com> / #ifndef _CS5536_H #define _CS5536_H #include <linux/types.h> extern void _rdmsr(u32 msr, u32 hi, u32 lo); extern void _wrmsr(u32 msr, u32 hi, u32 lo); / * MSR module base / #define CS5536_SB_MSR_BASE (0x00000000) #define CS5536_GLIU_MSR_BASE (0x10000000) #define CS5536_ILLEGAL_MSR_BASE (0x20000000) #define CS5536_USB_MSR_BASE (0x40000000) #define CS5536_IDE_MSR_BASE (0x60000000) #define CS5536_DIVIL_MSR_BASE (0x80000000) #define CS5536_ACC_MSR_BASE (0xa0000000) #define CS5536_UNUSED_MSR_BASE (0xc0000000) #define CS5536_GLCP_MSR_BASE (0xe0000000) #define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE \| (offset)) #define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE \| (offset)) #define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE \| (offset)) #define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE \| (offset)) #define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE \| (offset)) #define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE \| (offset)) #define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE \| (offset)) #define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE \| (offset)) #define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE \| (offset)) / * BAR SPACE OF VIRTUAL PCI : * range for pci probe use, length is the actual size. / / IO space for all DIVIL modules / #define CS5536_IRQ_RANGE 0xffffffe0 / USERD FOR PCI PROBE / #define CS5536_IRQ_LENGTH 0x20 / THE REGS ACTUAL LENGTH / #define CS5536_SMB_RANGE 0xfffffff8 #define CS5536_SMB_LENGTH 0x08 #define CS5536_GPIO_RANGE 0xffffff00 #define CS5536_GPIO_LENGTH 0x100 #define CS5536_MFGPT_RANGE 0xffffffc0 #define CS5536_MFGPT_LENGTH 0x40 #define CS5536_ACPI_RANGE 0xffffffe0 #define CS5536_ACPI_LENGTH 0x20 #define CS5536_PMS_RANGE 0xffffff80 #define CS5536_PMS_LENGTH 0x80 / IO space for IDE / #define CS5536_IDE_RANGE 0xfffffff0 #define CS5536_IDE_LENGTH 0x10 / IO space for ACC / #define CS5536_ACC_RANGE 0xffffff80 #define CS5536_ACC_LENGTH 0x80 / MEM space for ALL USB modules / #define CS5536_OHCI_RANGE 0xfffff000 #define CS5536_OHCI_LENGTH 0x1000 #define CS5536_EHCI_RANGE 0xfffff000 #define CS5536_EHCI_LENGTH 0x1000 / * PCI MSR ACCESS / #define PCI_MSR_CTRL 0xF0 #define PCI_MSR_ADDR 0xF4 #define PCI_MSR_DATA_LO 0xF8 #define PCI_MSR_DATA_HI 0xFC /************* MSR **************************/ / * GLIU STANDARD MSR / #define GLIU_CAP 0x00 #define GLIU_CONFIG 0x01 #define GLIU_SMI 0x02 #define GLIU_ERROR 0x03 #define GLIU_PM 0x04 #define GLIU_DIAG 0x05 / * GLIU SPEC. MSR / #define GLIU_P2D_BM0 0x20 #define GLIU_P2D_BM1 0x21 #define GLIU_P2D_BM2 0x22 #define GLIU_P2D_BMK0 0x23 #define GLIU_P2D_BMK1 0x24 #define GLIU_P2D_BM3 0x25 #define GLIU_P2D_BM4 0x26 #define GLIU_COH 0x80 #define GLIU_PAE 0x81 #define GLIU_ARB 0x82 #define GLIU_ASMI 0x83 #define GLIU_AERR 0x84 #define GLIU_DEBUG 0x85 #define GLIU_PHY_CAP 0x86 #define GLIU_NOUT_RESP 0x87 #define GLIU_NOUT_WDATA 0x88 #define GLIU_WHOAMI 0x8B #define GLIU_SLV_DIS 0x8C #define GLIU_IOD_BM0 0xE0 #define GLIU_IOD_BM1 0xE1 #define GLIU_IOD_BM2 0xE2 #define GLIU_IOD_BM3 0xE3 #define GLIU_IOD_BM4 0xE4 #define GLIU_IOD_BM5 0xE5 #define GLIU_IOD_BM6 0xE6 #define GLIU_IOD_BM7 0xE7 #define GLIU_IOD_BM8 0xE8 #define GLIU_IOD_BM9 0xE9 #define GLIU_IOD_SC0 0xEA #define GLIU_IOD_SC1 0xEB #define GLIU_IOD_SC2 0xEC #define GLIU_IOD_SC3 0xED #define GLIU_IOD_SC4 0xEE #define GLIU_IOD_SC5 0xEF #define GLIU_IOD_SC6 0xF0 #define GLIU_IOD_SC7 0xF1 / * SB STANDARD / #define SB_CAP 0x00 #define SB_CONFIG 0x01 #define SB_SMI 0x02 #define SB_ERROR 0x03 #define SB_MAR_ERR_EN 0x00000001 #define SB_TAR_ERR_EN 0x00000002 #define SB_RSVD_BIT1 0x00000004 #define SB_EXCEP_ERR_EN 0x00000008 #define SB_SYSE_ERR_EN 0x00000010 #define SB_PARE_ERR_EN 0x00000020 #define SB_TAS_ERR_EN 0x00000040 #define SB_MAR_ERR_FLAG 0x00010000 #define SB_TAR_ERR_FLAG 0x00020000 #define SB_RSVD_BIT2 0x00040000 #define SB_EXCEP_ERR_FLAG 0x00080000 #define SB_SYSE_ERR_FLAG 0x00100000 #define SB_PARE_ERR_FLAG 0x00200000 #define SB_TAS_ERR_FLAG 0x00400000 #define SB_PM 0x04 #define SB_DIAG 0x05 / * SB SPEC. / #define SB_CTRL 0x10 #define SB_R0 0x20 #define SB_R1 0x21 #define SB_R2 0x22 #define SB_R3 0x23 #define SB_R4 0x24 #define SB_R5 0x25 #define SB_R6 0x26 #define SB_R7 0x27 #define SB_R8 0x28 #define SB_R9 0x29 #define SB_R10 0x2A #define SB_R11 0x2B #define SB_R12 0x2C #define SB_R13 0x2D #define SB_R14 0x2E #define SB_R15 0x2F / * GLCP STANDARD / #define GLCP_CAP 0x00 #define GLCP_CONFIG 0x01 #define GLCP_SMI 0x02 #define GLCP_ERROR 0x03 #define GLCP_PM 0x04 #define GLCP_DIAG 0x05 / * GLCP SPEC. / #define GLCP_CLK_DIS_DELAY 0x08 #define GLCP_PM_CLK_DISABLE 0x09 #define GLCP_GLB_PM 0x0B #define GLCP_DBG_OUT 0x0C #define GLCP_RSVD1 0x0D #define GLCP_SOFT_COM 0x0E #define SOFT_BAR_SMB_FLAG 0x00000001 #define SOFT_BAR_GPIO_FLAG 0x00000002 #define SOFT_BAR_MFGPT_FLAG 0x00000004 #define SOFT_BAR_IRQ_FLAG 0x00000008 #define SOFT_BAR_PMS_FLAG 0x00000010 #define SOFT_BAR_ACPI_FLAG 0x00000020 #define SOFT_BAR_IDE_FLAG 0x00000400 #define SOFT_BAR_ACC_FLAG 0x00000800 #define SOFT_BAR_OHCI_FLAG 0x00001000 #define SOFT_BAR_EHCI_FLAG 0x00002000 #define GLCP_RSVD2 0x0F #define GLCP_CLK_OFF 0x10 #define GLCP_CLK_ACTIVE 0x11 #define GLCP_CLK_DISABLE 0x12 #define GLCP_CLK4ACK 0x13 #define GLCP_SYS_RST 0x14 #define GLCP_RSVD3 0x15 #define GLCP_DBG_CLK_CTRL 0x16 #define GLCP_CHIP_REV_ID 0x17 / PIC / #define PIC_YSEL_LOW 0x20 #define PIC_YSEL_LOW_USB_SHIFT 8 #define PIC_YSEL_LOW_ACC_SHIFT 16 #define PIC_YSEL_LOW_FLASH_SHIFT 24 #define PIC_YSEL_HIGH 0x21 #define PIC_ZSEL_LOW 0x22 #define PIC_ZSEL_HIGH 0x23 #define PIC_IRQM_PRIM 0x24 #define PIC_IRQM_LPC 0x25 #define PIC_XIRR_STS_LOW 0x26 #define PIC_XIRR_STS_HIGH 0x27 #define PCI_SHDW 0x34 / * DIVIL STANDARD / #define DIVIL_CAP 0x00 #define DIVIL_CONFIG 0x01 #define DIVIL_SMI 0x02 #define DIVIL_ERROR 0x03 #define DIVIL_PM 0x04 #define DIVIL_DIAG 0x05 / * DIVIL SPEC. / #define DIVIL_LBAR_IRQ 0x08 #define DIVIL_LBAR_KEL 0x09 #define DIVIL_LBAR_SMB 0x0B #define DIVIL_LBAR_GPIO 0x0C #define DIVIL_LBAR_MFGPT 0x0D #define DIVIL_LBAR_ACPI 0x0E #define DIVIL_LBAR_PMS 0x0F #define DIVIL_LEG_IO 0x14 #define DIVIL_BALL_OPTS 0x15 #define DIVIL_SOFT_IRQ 0x16 #define DIVIL_SOFT_RESET 0x17 / MFGPT / #define MFGPT_IRQ 0x28 / * IDE STANDARD / #define IDE_CAP 0x00 #define IDE_CONFIG 0x01 #define IDE_SMI 0x02 #define IDE_ERROR 0x03 #define IDE_PM 0x04 #define IDE_DIAG 0x05 / * IDE SPEC. / #define IDE_IO_BAR 0x08 #define IDE_CFG 0x10 #define IDE_DTC 0x12 #define IDE_CAST 0x13 #define IDE_ETC 0x14 #define IDE_INTERNAL_PM 0x15 / * ACC STANDARD / #define ACC_CAP 0x00 #define ACC_CONFIG 0x01 #define ACC_SMI 0x02 #define ACC_ERROR 0x03 #define ACC_PM 0x04 #define ACC_DIAG 0x05 / * USB STANDARD / #define USB_CAP 0x00 #define USB_CONFIG 0x01 #define USB_SMI 0x02 #define USB_ERROR 0x03 #define USB_PM 0x04 #define USB_DIAG 0x05 / * USB SPEC. / #define USB_OHCI 0x08 #define USB_EHCI 0x09 /*************** NATIVE ************************/ / GPIO : I/O SPACE; REG : 32BITS / #define GPIOL_OUT_VAL 0x00 #define GPIOL_OUT_EN 0x04 #endif / _CS5536_H / PK��k��ZCW��cs5536/cs5536_pci.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * the definition file of cs5536 Virtual Support Module(VSM). * pci configuration space can be accessed through the VSM, so * there is no need of the MSR read/write now, except the spec. * MSR registers which are not implemented yet. * * Copyright (C) 2007 Lemote Inc. * Author : jlliu, liujl@lemote.com / #ifndef _CS5536_PCI_H #define _CS5536_PCI_H #include <linux/types.h> #include <linux/pci_regs.h> extern void cs5536_pci_conf_write4(int function, int reg, u32 value); extern u32 cs5536_pci_conf_read4(int function, int reg); #define CS5536_ACC_INTR 9 #define CS5536_IDE_INTR 14 #define CS5536_USB_INTR 11 #define CS5536_MFGPT_INTR 5 #define CS5536_UART1_INTR 4 #define CS5536_UART2_INTR 3 /*********** PCI BUS DEVICE FUNCTION ************/ / * PCI bus device function / #define PCI_BUS_CS5536 0 #define PCI_IDSEL_CS5536 14 /******* STANDARD PCI-2.2 EXPANSION *************/ / * PCI configuration space * we have to virtualize the PCI configure space head, so we should * define the necessary IDs and some others. / / CONFIG of PCI VENDOR ID/ #define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ (((mod_dev_id) << 16) \| (sys_vendor_id)) / VENDOR ID / #define CS5536_VENDOR_ID 0x1022 / DEVICE ID / #define CS5536_ISA_DEVICE_ID 0x2090 #define CS5536_IDE_DEVICE_ID 0x209a #define CS5536_ACC_DEVICE_ID 0x2093 #define CS5536_OHCI_DEVICE_ID 0x2094 #define CS5536_EHCI_DEVICE_ID 0x2095 / CLASS CODE : CLASS SUB-CLASS INTERFACE / #define CS5536_ISA_CLASS_CODE 0x060100 #define CS5536_IDE_CLASS_CODE 0x010180 #define CS5536_ACC_CLASS_CODE 0x040100 #define CS5536_OHCI_CLASS_CODE 0x0C0310 #define CS5536_EHCI_CLASS_CODE 0x0C0320 / BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE / #define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ ((PCI_NONE_BIST << 24) \| ((header_type) << 16) \ \| ((latency_timer) << 8) \| PCI_NORMAL_CACHE_LINE_SIZE); #define PCI_NONE_BIST 0x00 / RO not implemented yet. / #define PCI_BRIDGE_HEADER_TYPE 0x80 / RO / #define PCI_NORMAL_HEADER_TYPE 0x00 #define PCI_NORMAL_LATENCY_TIMER 0x00 #define PCI_NORMAL_CACHE_LINE_SIZE 0x08 / RW / / BAR / #define PCI_BAR0_REG 0x10 #define PCI_BAR1_REG 0x14 #define PCI_BAR2_REG 0x18 #define PCI_BAR3_REG 0x1c #define PCI_BAR4_REG 0x20 #define PCI_BAR5_REG 0x24 #define PCI_BAR_RANGE_MASK 0xFFFFFFFF / CARDBUS CIS POINTER / #define PCI_CARDBUS_CIS_POINTER 0x00000000 / SUBSYSTEM VENDOR ID / #define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID / SUBSYSTEM ID / #define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID #define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID #define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID #define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID #define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID / EXPANSION ROM BAR / #define PCI_EXPANSION_ROM_BAR 0x00000000 / CAPABILITIES POINTER / #define PCI_CAPLIST_POINTER 0x00000000 #define PCI_CAPLIST_USB_POINTER 0x40 / INTERRUPT / #define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ ((PCI_MAX_LATENCY << 24) \| (PCI_MIN_GRANT << 16) \| \ ((pin) << 8) \| (mod_intr)) #define PCI_MAX_LATENCY 0x40 #define PCI_MIN_GRANT 0x00 #define PCI_DEFAULT_PIN 0x01 /******** EXPANSION PCI REG *********************/ / * ISA EXPANSION / #define PCI_UART1_INT_REG 0x50 #define PCI_UART2_INT_REG 0x54 #define PCI_ISA_FIXUP_REG 0x58 / * IDE EXPANSION / #define PCI_IDE_CFG_REG 0x40 #define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF #define PCI_IDE_DTC_REG 0x48 #define PCI_IDE_CAST_REG 0x4C #define PCI_IDE_ETC_REG 0x50 #define PCI_IDE_PM_REG 0x54 #define PCI_IDE_INT_REG 0x60 / * ACC EXPANSION / #define PCI_ACC_INT_REG 0x50 / * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI / #define PCI_OHCI_PM_REG 0x40 #define PCI_OHCI_INT_REG 0x50 / * EHCI EXPANSION / #define PCI_EHCI_LEGSMIEN_REG 0x50 #define PCI_EHCI_LEGSMISTS_REG 0x54 #define PCI_EHCI_FLADJ_REG 0x60 #endif / _CS5536_PCI_H_ / PK��k��ZaW�S��cs5536/cs5536_vsm.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * the read/write interfaces for Virtual Support Module(VSM) * * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> / #ifndef _CS5536_VSM_H #define _CS5536_VSM_H #include <linux/types.h> typedef void (cs5536_pci_vsm_write)(int reg, u32 value); typedef u32 (cs5536_pci_vsm_read)(int reg); #define DECLARE_CS5536_MODULE(name) \ extern void pci_##name##_write_reg(int reg, u32 value); \ extern u32 pci_##name##_read_reg(int reg); / ide module / DECLARE_CS5536_MODULE(ide) / acc module / DECLARE_CS5536_MODULE(acc) / ohci module / DECLARE_CS5536_MODULE(ohci) / isa module / DECLARE_CS5536_MODULE(isa) / ehci module / DECLARE_CS5536_MODULE(ehci) #endif / _CS5536_VSM_H / PK��k��Z��!Y��cs5536/cs5536_mfgpt.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / / * cs5536 mfgpt header file / #ifndef _CS5536_MFGPT_H #define _CS5536_MFGPT_H #include <cs5536/cs5536.h> #include <cs5536/cs5536_pci.h> #ifdef CONFIG_CS5536_MFGPT extern void setup_mfgpt0_timer(void); extern void disable_mfgpt0_counter(void); extern void enable_mfgpt0_counter(void); #else static inline void __maybe_unused setup_mfgpt0_timer(void) { } static inline void __maybe_unused disable_mfgpt0_counter(void) { } static inline void __maybe_unused enable_mfgpt0_counter(void) { } #endif #define MFGPT_TICK_RATE 14318000 #define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) #define MFGPT_BASE mfgpt_base #define MFGPT0_CMP2 (MFGPT_BASE + 2) #define MFGPT0_CNT (MFGPT_BASE + 4) #define MFGPT0_SETUP (MFGPT_BASE + 6) #endif /!_CS5536_MFGPT_H / PK��k��Z�6g}��pci.hnu��[��/ SPDX-License-Identifier: GPL-2.0-or-later / / * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com> / #ifndef __ASM_MACH_LOONGSON2EF_PCI_H_ #define __ASM_MACH_LOONGSON2EF_PCI_H_ extern struct pci_ops loongson_pci_ops; / this is an offset from mips_io_port_base / #define LOONGSON_PCI_IO_START 0x00004000UL #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG / * we use address window2 to map cpu address space to pci space * window2: cpu [1G, 2G] -> pci [1G, 2G] * why not use window 0 & 1? because they are used by cpu when booting. * window0: cpu [0, 256M] -> ddr [0, 256M] * window1: cpu [256M, 512M] -> pci [256M, 512M] / / the smallest LOONGSON_CPU_MEM_SRC can be 512M / #define LOONGSON_CPU_MEM_SRC 0x40000000ul / 1G / #define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC #define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST #define LOONGSON_PCI_MEM_END (0x80000000ul-1) / 2G / #define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ LOONGSON_PCI_MEM_START + 1) #else / loongson2f/32bit & loongson2e / / this pci memory space is mapped by pcimap in pci.c / #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE #define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 2) /* this is an offset from mips_io_port_base / #define LOONGSON_PCI_IO_START 0x00004000UL #endif / !CONFIG_CPU_SUPPORTS_ADDRWINCFG / #endif / !__ASM_MACH_LOONGSON2EF_PCI_H_ / PK��k��Z��F,��,�� loongson.hnu��[��/ SPDX-License-Identifier: GPL-2.0-or-later / / * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> / #ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H #define __ASM_MACH_LOONGSON2EF_LOONGSON_H #include <linux/io.h> #include <linux/init.h> #include <linux/irq.h> / loongson internal northbridge initialization / extern void bonito_irq_init(void); / machine-specific reboot/halt operation / extern void mach_prepare_reboot(void); extern void mach_prepare_shutdown(void); / environment arguments from bootloader / extern u32 cpu_clock_freq; extern u32 memsize, highmemsize; / loongson-specific command line, env and memory initialization / extern void __init prom_init_memory(void); extern void __init prom_init_machtype(void); extern void __init prom_init_env(void); #ifdef CONFIG_LOONGSON_UART_BASE extern unsigned long _loongson_uart_base, loongson_uart_base; extern void prom_init_loongson_uart_base(void); #endif static inline void prom_init_uart_base(void) { #ifdef CONFIG_LOONGSON_UART_BASE prom_init_loongson_uart_base(); #endif } / irq operation functions / extern void bonito_irqdispatch(void); extern void __init bonito_irq_init(void); extern void __init mach_init_irq(void); extern void mach_irq_dispatch(unsigned int pending); extern int mach_i8259_irq(void); / We need this in some places... / #define delay() ({ \ int x; \ for (x = 0; x < 100000; x++) \ __asm__ __volatile__(""); \ }) #define LOONGSON_REG(x) \ ((volatile u32 )((char )CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) #define LOONGSON_IRQ_BASE 32 #define LOONGSON_FLASH_BASE 0x1c000000 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M / #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) #define LOONGSON_LIO0_BASE 0x1e000000 #define LOONGSON_LIO0_SIZE 0x01C00000 / 28M / #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) #define LOONGSON_BOOT_BASE 0x1fc00000 #define LOONGSON_BOOT_SIZE 0x00100000 / 1M / #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) #define LOONGSON_REG_BASE 0x1fe00000 #define LOONGSON_REG_SIZE 0x00100000 / 256Bytes + 256Bytes + ??? / #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) #define LOONGSON_LIO1_BASE 0x1ff00000 #define LOONGSON_LIO1_SIZE 0x00100000 / 1M / #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) #define LOONGSON_PCILO0_BASE 0x10000000 #define LOONGSON_PCILO1_BASE 0x14000000 #define LOONGSON_PCILO2_BASE 0x18000000 #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE #define LOONGSON_PCILO_SIZE 0x0c000000 / 64M * 3 / #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) #define LOONGSON_PCICFG_BASE 0x1fe80000 #define LOONGSON_PCICFG_SIZE 0x00000800 / 2K / #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) #define LOONGSON_PCIIO_BASE 0x1fd00000 #define LOONGSON_PCIIO_SIZE 0x00100000 / 1M / #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) / Loongson Register Bases / #define LOONGSON_PCICONFIGBASE 0x00 #define LOONGSON_REGBASE 0x100 / PCI Configuration Registers / #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) #define LOONGSON_PCICMD_PERR_CLR 0x80000000 #define LOONGSON_PCICMD_SERR_CLR 0x40000000 #define LOONGSON_PCICMD_MABORT_CLR 0x20000000 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000 #define LOONGSON_PCICMD_MPERR_CLR 0x01000000 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040 #define LOONGSON_PCICMD_ASTEPEN 0x00000080 #define LOONGSON_PCICMD_SERREN 0x00000100 #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 / Loongson h/w Configuration / #define LOONGSON_GENCFG_OFFSET 0x4 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) #define LOONGSON_GENCFG_DEBUGMODE 0x00000001 #define LOONGSON_GENCFG_SNOOPEN 0x00000002 #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 #define LOONGSON_GENCFG_BYTESWAP 0x00000040 #define LOONGSON_GENCFG_UNCACHED 0x00000080 #define LOONGSON_GENCFG_PREFETCHEN 0x00000100 #define LOONGSON_GENCFG_WBEHINDEN 0x00000200 #define LOONGSON_GENCFG_CACHEALG 0x00000c00 #define LOONGSON_GENCFG_CACHEALG_SHIFT 10 #define LOONGSON_GENCFG_PCIQUEUE 0x00001000 #define LOONGSON_GENCFG_CACHESTOP 0x00002000 #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 #define LOONGSON_GENCFG_BUSERREN 0x00008000 #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 / PCI address map control / #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) / GPIO Regs - r/w / #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) / ICU Configuration Regs - r/w / #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) / ICU Enable Regs - IntEn & IntISR are r/o. / #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) / ICU / #define LOONGSON_ICU_MBOXES 0x0000000f #define LOONGSON_ICU_MBOXES_SHIFT 0 #define LOONGSON_ICU_DMARDY 0x00000010 #define LOONGSON_ICU_DMAEMPTY 0x00000020 #define LOONGSON_ICU_COPYRDY 0x00000040 #define LOONGSON_ICU_COPYEMPTY 0x00000080 #define LOONGSON_ICU_COPYERR 0x00000100 #define LOONGSON_ICU_PCIIRQ 0x00000200 #define LOONGSON_ICU_MASTERERR 0x00000400 #define LOONGSON_ICU_SYSTEMERR 0x00000800 #define LOONGSON_ICU_DRAMPERR 0x00001000 #define LOONGSON_ICU_RETRYERR 0x00002000 #define LOONGSON_ICU_GPIOS 0x01ff0000 #define LOONGSON_ICU_GPIOS_SHIFT 16 #define LOONGSON_ICU_GPINS 0x7e000000 #define LOONGSON_ICU_GPINS_SHIFT 25 #define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) #define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) #define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) / PCI prefetch window base & mask / #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) / PCI_Hit_Sel_ / #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) / PXArb Config & Status / #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) / Chip Config registor of each physical cpu package, PRid >= Loongson-2F / #define LOONGSON_CHIPCFG (void __iomem )TO_UNCAC(0x1fc00180) /* pcimap / #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)6)) #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ #include <linux/cpufreq.h> extern struct cpufreq_frequency_table loongson2_clockmod_table[]; extern int loongson2_cpu_set_rate(unsigned long rate_khz); #endif /* * address windows configuration module * * loongson2e do not have this module / #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG / address window config module base address / #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul #define LOONGSON_ADDRWINCFG_SIZE 0x180 extern unsigned long _loongson_addrwincfg_base; #define LOONGSON_ADDRWINCFG(offset) \ ((volatile u64 )(_loongson_addrwincfg_base + (offset))) #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) #define ADDRWIN_WIN0 0 #define ADDRWIN_WIN1 1 #define ADDRWIN_WIN2 2 #define ADDRWIN_WIN3 3 #define ADDRWIN_MAP_DST_DDR 0 #define ADDRWIN_MAP_DST_PCI 1 #define ADDRWIN_MAP_DST_LIO 1 / * s: CPU, PCIDMA * d: DDR, PCI, LIO * win: 0, 1, 2, 3 * src: map source * dst: map destination * size: ~mask + 1 / #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ s##_WIN##w##_BASE = (src); \ s##_WIN##w##_MMAP = (dst) \| ADDRWIN_MAP_DST_##d; \ s##_WIN##w##_MASK = ~(size-1); \ } while (0) #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) #endif / ! CONFIG_CPU_SUPPORTS_ADDRWINCFG / #endif / __ASM_MACH_LOONGSON2EF_LOONGSON_H / PK��k��Z��spaces.hnu��[��/ SPDX-License-Identifier: GPL-2.0 / #ifndef __ASM_MACH_LOONGSON2EF_SPACES_H_ #define __ASM_MACH_LOONGSON2EF_SPACES_H_ #if defined(CONFIG_64BIT) #define CAC_BASE _AC(0x9800000000000000, UL) #endif / CONFIG_64BIT / #include <asm/mach-generic/spaces.h> #endif PK��k��Z�Ե�� machine.hnu��[��/ SPDX-License-Identifier: GPL-2.0-or-later / / * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> / #ifndef __ASM_MACH_LOONGSON2EF_MACHINE_H #define __ASM_MACH_LOONGSON2EF_MACHINE_H #ifdef CONFIG_LEMOTE_FULOONG2E #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E #endif / use fuloong2f as the default machine of LEMOTE_MACH2F / #ifdef CONFIG_LEMOTE_MACH2F #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F #endif #endif / __ASM_MACH_LOONGSON2EF_MACHINE_H / PK��k��Z�ѷW^��^��mem.hnu��[��/ SPDX-License-Identifier: GPL-2.0-or-later / / * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzhangjin@gmail.com> / #ifndef __ASM_MACH_LOONGSON2EF_MEM_H #define __ASM_MACH_LOONGSON2EF_MEM_H / * high memory space * * in loongson2e, starts from 512M * in loongson2f, starts from 2G 256M / #ifdef CONFIG_CPU_LOONGSON2E #define LOONGSON_HIGHMEM_START 0x20000000 #else #define LOONGSON_HIGHMEM_START 0x90000000 #endif / * the peripheral registers(MMIO): * * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. / #define LOONGSON_MMIO_MEM_START 0x10000000 #ifdef CONFIG_CPU_LOONGSON2E #define LOONGSON_MMIO_MEM_END 0x20000000 #else #define LOONGSON_MMIO_MEM_END 0x80000000 #endif #endif / __ASM_MACH_LOONGSON2EF_MEM_H / PK��k��Z��&k��cpu-feature-overrides.hnu��[��/ SPDX-License-Identifier: GPL-2.0-or-later / / * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com> * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> * * reference: /proc/cpuinfo, * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), * arch/mips/kernel/proc.c(show_cpuinfo), * loongson2f user manual. / #ifndef __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H #define __ASM_MACH_LOONGSON2EF_CPU_FEATURE_OVERRIDES_H #define cpu_has_32fpr 1 #define cpu_has_3k_cache 0 #define cpu_has_4k_cache 1 #define cpu_has_4kex 1 #define cpu_has_64bits 1 #define cpu_has_cache_cdex_p 0 #define cpu_has_cache_cdex_s 0 #define cpu_has_counter 1 #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) #define cpu_has_divec 0 #define cpu_has_ejtag 0 #define cpu_has_inclusive_pcaches 1 #define cpu_has_llsc 1 #define cpu_has_mcheck 0 #define cpu_has_mdmx 0 #define cpu_has_mips16 0 #define cpu_has_mips16e2 0 #define cpu_has_mips3d 0 #define cpu_has_mipsmt 0 #define cpu_has_smartmips 0 #define cpu_has_tlb 1 #define cpu_has_tx39_cache 0 #define cpu_has_vce 0 #define cpu_has_veic 0 #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 #endif / __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */ PK��k��Z�V��cs5536/cs5536.hnu��[��PK��k��ZCW��'��cs5536/cs5536_pci.hnu��[��PK��k��ZaW�S��-��cs5536/cs5536_vsm.hnu��[��PK��k��Z��!Y��H0��cs5536/cs5536_mfgpt.hnu��[��PK��k��Z�6g}��3��pci.hnu��[��PK��k��Z��F,��,�� 9��loongson.hnu��[��PK��k��Z��e��spaces.hnu��[��PK��k��Z�Ե�� g��machine.hnu��[��PK��k��Z�ѷW^��^��3i��mem.hnu��[��PK��k��Z��&k��l��cpu-feature-overrides.hnu��[��PK�� r��

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