File manager - Edit - /home/newsbmcs.com/public_html/static/img/logo/mach.zip
Back
PK �h�ZJ�8�� � shmin.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SHMIN_H #define __ASM_SH_SHMIN_H #define SHMIN_IO_BASE 0xb0000000UL #define SHMIN_NE_IRQ IRQ2_IRQ #define SHMIN_NE_BASE 0x300 #endif PK �h�Z|� ̤ � sh7763rdp.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_SH7763RDP_H #define __ASM_SH_SH7763RDP_H /* * linux/include/asm-sh/sh7763drp.h * * Copyright (C) 2008 Renesas Solutions * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> */ #include <asm/addrspace.h> /* clock control */ #define MSTPCR1 0xFFC80038 /* PORT */ #define PORT_PSEL0 0xFFEF0070 #define PORT_PSEL1 0xFFEF0072 #define PORT_PSEL2 0xFFEF0074 #define PORT_PSEL3 0xFFEF0076 #define PORT_PSEL4 0xFFEF0078 #define PORT_PACR 0xFFEF0000 #define PORT_PCCR 0xFFEF0004 #define PORT_PFCR 0xFFEF000A #define PORT_PGCR 0xFFEF000C #define PORT_PHCR 0xFFEF000E #define PORT_PICR 0xFFEF0010 #define PORT_PJCR 0xFFEF0012 #define PORT_PKCR 0xFFEF0014 #define PORT_PLCR 0xFFEF0016 #define PORT_PMCR 0xFFEF0018 #define PORT_PNCR 0xFFEF001A /* FPGA */ #define CPLD_BOARD_ID_ERV_REG 0xB1000000 #define CPLD_CPLD_CMD_REG 0xB1000006 /* * USB SH7763RDP board can use Host only. */ #define USB_USBHSC 0xFFEC80f0 /* arch/sh/boards/renesas/sh7763rdp/irq.c */ void init_sh7763rdp_IRQ(void); int sh7763rdp_irq_demux(int irq); #define __IO_PREFIX sh7763rdp #include <asm/io_generic.h> #endif /* __ASM_SH_SH7763RDP_H */ PK �h�Z� �]� � romimage.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifdef __ASSEMBLY__ /* do nothing here by default */ #else /* __ASSEMBLY__ */ static inline void mmcif_update_progress(int nr) { } #endif /* __ASSEMBLY__ */ PK �h�Z�>��� � microdev.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * linux/include/asm-sh/microdev.h * * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) * * Definitions for the SuperH SH4-202 MicroDev board. */ #ifndef __ASM_SH_MICRODEV_H #define __ASM_SH_MICRODEV_H extern void init_microdev_irq(void); extern void microdev_print_fpga_intc_status(void); /* * The following are useful macros for manipulating the interrupt * controller (INTC) on the CPU-board FPGA. should be noted that there * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - * these are two different things, both of which need to be prorammed to * correctly route - unfortunately, they have the same name and * abbreviations! */ #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ /* * The following are the IRQ numbers for the Linux Kernel for external * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. */ #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ /* * The following are the IRQ numbers for the INTC on the FPGA for * external interrupts. i.e. the bits in the INTC registers in the * FPGA. */ #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ #define MICRODEV_IRQ_PCI_INTA 8 #define MICRODEV_IRQ_PCI_INTB 9 #define MICRODEV_IRQ_PCI_INTC 10 #define MICRODEV_IRQ_PCI_INTD 11 #define __IO_PREFIX microdev #include <asm/io_generic.h> #endif /* __ASM_SH_MICRODEV_H */ PK �h�Z�'yn� � mangle-port.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * SH version cribbed from the MIPS copy: * * Copyright (C) 2003, 2004 Ralf Baechle */ #ifndef __MACH_COMMON_MANGLE_PORT_H #define __MACH_COMMON_MANGLE_PORT_H /* * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; * less sane hardware forces software to fiddle with this... * * Regardless, if the host bus endianness mismatches that of PCI/ISA, then * you can't have the numerical value of data and byte addresses within * multibyte quantities both preserved at the same time. Hence two * variations of functions: non-prefixed ones that preserve the value * and prefixed ones that preserve byte addresses. The latters are * typically used for moving raw data between a peripheral and memory (cf. * string I/O functions), hence the "__mem_" prefix. */ #if defined(CONFIG_SWAP_IO_SPACE) # define ioswabb(x) (x) # define __mem_ioswabb(x) (x) # define ioswabw(x) le16_to_cpu(x) # define __mem_ioswabw(x) (x) # define ioswabl(x) le32_to_cpu(x) # define __mem_ioswabl(x) (x) # define ioswabq(x) le64_to_cpu(x) # define __mem_ioswabq(x) (x) #else # define ioswabb(x) (x) # define __mem_ioswabb(x) (x) # define ioswabw(x) (x) # define __mem_ioswabw(x) cpu_to_le16(x) # define ioswabl(x) (x) # define __mem_ioswabl(x) cpu_to_le32(x) # define ioswabq(x) (x) # define __mem_ioswabq(x) cpu_to_le32(x) #endif #endif /* __MACH_COMMON_MANGLE_PORT_H */ PK �h�Z�aS� � sh2007.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_SH2007_H #define __MACH_SH2007_H #define CS5BCR 0xff802050 #define CS5WCR 0xff802058 #define CS5PCR 0xff802070 #define BUS_SZ8 1 #define BUS_SZ16 2 #define BUS_SZ32 3 #define PCMCIA_IODYN 1 #define PCMCIA_ATA 0 #define PCMCIA_IO8 2 #define PCMCIA_IO16 3 #define PCMCIA_COMM8 4 #define PCMCIA_COMM16 5 #define PCMCIA_ATTR8 6 #define PCMCIA_ATTR16 7 #define TYPE_SRAM 0 #define TYPE_PCMCIA 4 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWW5 0 #define IWW6 3 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRWD5 2 #define IWRWD6 2 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRWS5 2 #define IWRWS6 2 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRRD5 2 #define IWRRD6 2 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ #define IWRRS5 0 #define IWRRS6 2 /* burst count (0-3:4,8,16,32) */ #define BST5 0 #define BST6 0 /* bus size */ #define SZ5 BUS_SZ16 #define SZ6 BUS_SZ16 /* RD hold for SRAM (0-1:0,1) */ #define RDSPL5 0 #define RDSPL6 0 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ #define BW5 0 #define BW6 0 /* Multiplex (0-1:0,1) */ #define MPX5 0 #define MPX6 0 /* device type */ #define TYPE5 TYPE_PCMCIA #define TYPE6 TYPE_PCMCIA /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define ADS5 0 #define ADS6 0 /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define ADH5 0 #define ADH6 0 /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define RDS5 0 #define RDS6 0 /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define RDH5 0 #define RDH6 0 /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define WTS5 0 #define WTS6 0 /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ #define WTH5 0 #define WTH6 0 /* BS hold (0-1:1,2) */ #define BSH5 0 #define BSH6 0 /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ #define IW5 6 /* 60ns PIO mode 4 */ #define IW6 15 /* 250ns */ #define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ #define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ #define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ #define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ #define PCIW5 12 /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ #define TEDA5 2 /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ #define TEDB5 4 /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ #define TEHA5 2 /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ #define TEHB5 3 #define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) #define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) #define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ (TEDB5<<8)|(TEHA5<<4)|TEHB5) #define SMC0_BASE 0xb0800000 /* eth0 */ #define SMC1_BASE 0xb0900000 /* eth1 */ #define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ #define IDE_BASE 0xb4000000 /* IDE */ #define PC104_IO_BASE 0xb8000000 #define PC104_MEM_BASE 0xba000000 #define SMC_IO_SIZE 0x100 #define CF_OFFSET 0x1f0 #define IDE_OFFSET 0x170 #endif /* __MACH_SH2007_H */ PK �h�Z.V� � sdk7780.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_SDK7780_H #define __ASM_SH_RENESAS_SDK7780_H /* * linux/include/asm-sh/sdk7780.h * * Renesas Solutions SH7780 SDK Support * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk> */ #include <linux/sh_intc.h> #include <asm/addrspace.h> /* Box specific addresses. */ #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ #define PA_ROM 0xa0000000 /* EPROM */ #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ #define PA_FROM 0xa0800000 /* Flash-ROM */ #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */ #define PA_EXT1 0xa4000000 #define PA_EXT1_SIZE 0x04000000 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ #define PA_SDRAM_SIZE 0x08000000 #define PA_EXT4 0xb0000000 #define PA_EXT4_SIZE 0x04000000 #define PA_EXT_USER PA_EXT4 /* User Expansion Space */ #define PA_PERIPHERAL PA_AREA5_IO /* SRAM/Reserved */ #define PA_RESERVED (PA_PERIPHERAL + 0) /* FPGA base address */ #define PA_FPGA (PA_PERIPHERAL + 0x01000000) /* SMC LAN91C111 */ #define PA_LAN (PA_PERIPHERAL + 0x01800000) #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ #define PA_LED FPGA_SLEDR #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ #define SDK7780_NR_IRL 15 /* IDE/ATA interrupt */ #define IRQ_CFCARD evt2irq(0x3c0) /* SMC interrupt */ #define IRQ_ETHERNET evt2irq(0x2c0) /* arch/sh/boards/renesas/sdk7780/irq.c */ void init_sdk7780_IRQ(void); #define __IO_PREFIX sdk7780 #include <asm/io_generic.h> #endif /* __ASM_SH_RENESAS_SDK7780_H */ PK �h�Z�)}' }' highlander.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_R7780RP_H #define __ASM_SH_RENESAS_R7780RP_H /* Box specific addresses. */ #define PA_NORFLASH_ADDR 0x00000000 #define PA_NORFLASH_SIZE 0x04000000 #if defined(CONFIG_SH_R7780MP) #define PA_BCR 0xa4000000 /* FPGA */ #define PA_SDPOW (-1) #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */ #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */ #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */ #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */ #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */ #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */ #define PA_PCICD (PA_BCR+0x0010) /* PCI Connector detect control */ #define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */ #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */ #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */ #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */ #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ #define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */ #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */ #define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */ #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */ #define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */ #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */ #define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */ #define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */ #define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */ #define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */ #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */ #define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */ #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */ #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */ #define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */ #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */ #define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */ #define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */ #define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */ #define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */ #define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */ #define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */ #define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */ #define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */ #define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */ #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */ #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */ #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */ #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */ #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */ #define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */ #define PA_POFF (PA_BCR+0x0800) /* System Power Off control */ #define PA_PMR (PA_BCR+0x0900) /* */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IVDR_CK_ON 8 /* iVDR Clock ON */ #elif defined(CONFIG_SH_R7780RP) #define PA_POFF (-1) #define PA_BCR 0xa5000000 /* FPGA */ #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ #define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */ #define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */ #define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */ #define PA_PCICD (PA_BCR+0x000a) /* PCI Connector detect control */ #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */ #define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */ #define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */ #define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */ #define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */ #define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */ #define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */ #define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */ #define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */ #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */ #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ #define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */ #define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */ #define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */ #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ #define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ #define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */ #define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */ #define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */ #define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */ #define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */ #define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */ #define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */ #define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */ #define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */ #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */ #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */ #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */ #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */ #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */ #define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */ #define PA_AX88796L 0xa5800400 /* AX88796L Area */ #define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IVDR_CK_ON 8 /* iVDR Clock ON */ #elif defined(CONFIG_SH_R7785RP) #define PA_BCR 0xa4000000 /* FPGA */ #define PA_SDPOW (-1) #define PA_PCISCR (PA_BCR+0x0000) #define PA_IRLPRA (PA_BCR+0x0002) #define PA_IRLPRB (PA_BCR+0x0004) #define PA_IRLPRC (PA_BCR+0x0006) #define PA_IRLPRD (PA_BCR+0x0008) #define IRLCNTR1 (PA_BCR+0x0010) #define PA_IRLPRE (PA_BCR+0x000a) #define PA_IRLPRF (PA_BCR+0x000c) #define PA_EXIRLCR (PA_BCR+0x000e) #define PA_IRLMCR1 (PA_BCR+0x0010) #define PA_IRLMCR2 (PA_BCR+0x0012) #define PA_IRLSSR1 (PA_BCR+0x0014) #define PA_IRLSSR2 (PA_BCR+0x0016) #define PA_CFTCR (PA_BCR+0x0100) #define PA_CFPCR (PA_BCR+0x0102) #define PA_PCICR (PA_BCR+0x0110) #define PA_IVDRCTL (PA_BCR+0x0112) #define PA_IVDRSR (PA_BCR+0x0114) #define PA_PDRSTCR (PA_BCR+0x0116) #define PA_POFF (PA_BCR+0x0120) #define PA_LCDCR (PA_BCR+0x0130) #define PA_TPCR (PA_BCR+0x0140) #define PA_TPCKCR (PA_BCR+0x0142) #define PA_TPRSTR (PA_BCR+0x0144) #define PA_TPXPDR (PA_BCR+0x0146) #define PA_TPYPDR (PA_BCR+0x0148) #define PA_GPIOPFR (PA_BCR+0x0150) #define PA_GPIODR (PA_BCR+0x0152) #define PA_OBLED (PA_BCR+0x0154) #define PA_SWSR (PA_BCR+0x0156) #define PA_VERREG (PA_BCR+0x0158) #define PA_SMCR (PA_BCR+0x0200) #define PA_SMSMADR (PA_BCR+0x0202) #define PA_SMMR (PA_BCR+0x0204) #define PA_SMSADR1 (PA_BCR+0x0206) #define PA_SMSADR32 (PA_BCR+0x0244) #define PA_SMTRDR1 (PA_BCR+0x0246) #define PA_SMTRDR16 (PA_BCR+0x0264) #define PA_CU3MDR (PA_BCR+0x0300) #define PA_CU5MDR (PA_BCR+0x0302) #define PA_MMSR (PA_BCR+0x0400) #define IVDR_CK_ON 4 /* iVDR Clock ON */ #endif #define HL_FPGA_IRQ_BASE 200 #define HL_NR_IRL 15 #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) #define IRQ_CF (HL_FPGA_IRQ_BASE + 1) #define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) #define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3) #define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4) #define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5) #define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6) #define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7) #define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8) #define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9) #define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10) #define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11) #define IRQ_TP (HL_FPGA_IRQ_BASE + 12) #define IRQ_RTC (HL_FPGA_IRQ_BASE + 13) #define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14) #define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) #define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) unsigned char *highlander_plat_irq_setup(void); #ifdef CONFIG_SH_R7785RP void highlander_plat_pinmux_setup(void); #else #define highlander_plat_pinmux_setup() do { } while (0) #endif #endif /* __ASM_SH_RENESAS_R7780RP */ PK �h�Z:�W�� � urquell.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_URQUELL_H #define __MACH_URQUELL_H /* * ------ 0x00000000 ------------------------------------ * CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH * -----+ 0x04000000 ------------------------------------ * CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH * -----+ 0x08000000 ------------------------------------ * CS2 | DDR3 * CS3 | * -----+ 0x10000000 ------------------------------------ * CS4 | PCIe * -----+ 0x14000000 ------------------------------------ * CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA * -----+ 0x18000000 ------------------------------------ * CS6 | ATA, NAND FLASH * -----+ 0x1c000000 ------------------------------------ * CS7 | SH7786 register * -----+------------------------------------------------ */ #define NOR_FLASH_ADDR 0x00000000 #define NOR_FLASH_SIZE 0x04000000 #define CS1_BASE 0x05000000 #define CS5_BASE 0x15000000 #define FPGA_BASE CS1_BASE #define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS) #define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS) #define SRSTR_OFS 0x0000 /* System reset register */ #define BDMR_OFS 0x0010 /* Board operating mode resister */ #define IRL0SR_OFS 0x0020 /* IRL0 Status register */ #define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */ #define IRL1SR_OFS 0x0040 /* IRL1 Status register */ #define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */ #define IRL2SR_OFS 0x0060 /* IRL2 Status register */ #define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */ #define IRL3SR_OFS 0x0080 /* IRL3 Status register */ #define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */ #define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */ #define SLEDR_OFS 0x0130 /* LED control resister */ #define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */ #define FPVERR_OFS 0x0150 /* FPGA Version register */ #define FPDATER_OFS 0x0160 /* FPGA Date register */ #define FPYEARR_OFS 0x0170 /* FPGA Year register */ #define TCLKCR_OFS 0x0180 /* TCLK Control register */ #define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */ #define FPODR_OFS 0x1010 /* Output port data register */ #define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */ #define FPINDR_OFS 0x1030 /* Input port data register */ #define MDSWMR_OFS 0x1040 /* MODE SW monitor register */ #define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */ #define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */ #define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */ #define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */ #define LATCHCR_OFS 0x3000 /* Latch control register */ #define LATCUAR_OFS 0x3010 /* Latch upper address register */ #define LATCLAR_OFS 0x3012 /* Latch lower address register */ #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */ #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */ #define CHARLED_OFS 0x2000 /* Character LED */ #endif /* __MACH_URQUELL_H */ PK �h�Ze��b magicpanelr2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/magicpanelr2.h * * Copyright (C) 2007 Markus Brunner, Mark Jonas * * I/O addresses and bitmasks for Magic Panel Release 2 board */ #ifndef __ASM_SH_MAGICPANELR2_H #define __ASM_SH_MAGICPANELR2_H #include <linux/gpio.h> #define __IO_PREFIX mpr2 #include <asm/io_generic.h> #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) #define PA_LED PORT_PADR /* LED */ /* BSC */ #define CMNCR 0xA4FD0000UL #define CS0BCR 0xA4FD0004UL #define CS2BCR 0xA4FD0008UL #define CS3BCR 0xA4FD000CUL #define CS4BCR 0xA4FD0010UL #define CS5ABCR 0xA4FD0014UL #define CS5BBCR 0xA4FD0018UL #define CS6ABCR 0xA4FD001CUL #define CS6BBCR 0xA4FD0020UL #define CS0WCR 0xA4FD0024UL #define CS2WCR 0xA4FD0028UL #define CS3WCR 0xA4FD002CUL #define CS4WCR 0xA4FD0030UL #define CS5AWCR 0xA4FD0034UL #define CS5BWCR 0xA4FD0038UL #define CS6AWCR 0xA4FD003CUL #define CS6BWCR 0xA4FD0040UL /* usb */ #define PORT_UTRCTL 0xA405012CUL #define PORT_UCLKCR_W 0xA40A0008UL #define INTC_ICR0 0xA414FEE0UL #define INTC_ICR1 0xA4140010UL #define INTC_ICR2 0xA4140012UL /* MTD */ #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL #define MPR2_MTD_KERNEL_SIZE 0x00200000UL #endif /* __ASM_SH_MAGICPANELR2_H */ PK �h�ZL�|�Y Y hp6xx.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2003, 2004, 2005 Andriy Skulysh */ #ifndef __ASM_SH_HP6XX_H #define __ASM_SH_HP6XX_H #include <linux/sh_intc.h> #define HP680_BTN_IRQ evt2irq(0x600) /* IRQ0_IRQ */ #define HP680_TS_IRQ evt2irq(0x660) /* IRQ3_IRQ */ #define HP680_HD64461_IRQ evt2irq(0x680) /* IRQ4_IRQ */ #define DAC_LCD_BRIGHTNESS 0 #define DAC_SPEAKER_VOLUME 1 #define PGDR_OPENED 0x01 #define PGDR_MAIN_BATTERY_OUT 0x04 #define PGDR_PLAY_BUTTON 0x08 #define PGDR_REWIND_BUTTON 0x10 #define PGDR_RECORD_BUTTON 0x20 #define PHDR_TS_PEN_DOWN 0x08 #define PJDR_LED_BLINK 0x02 #define PKDR_LED_GREEN 0x10 /* HP Palmtop 620lx/660lx speaker on/off */ #define PKDR_SPEAKER 0x20 #define SCPDR_TS_SCAN_ENABLE 0x20 #define SCPDR_TS_SCAN_Y 0x02 #define SCPDR_TS_SCAN_X 0x01 #define SCPCR_TS_ENABLE 0x405 #define SCPCR_TS_MASK 0xc0f #define ADC_CHANNEL_TS_Y 1 #define ADC_CHANNEL_TS_X 2 #define ADC_CHANNEL_BATTERY 3 #define ADC_CHANNEL_BACKUP 4 #define ADC_CHANNEL_CHARGE 5 /* HP Jornada 680/690 speaker on/off */ #define HD64461_GPADR_SPEAKER 0x01 #define HD64461_GPADR_PCMCIA0 (0x02|0x08) #define HD64461_GPBDR_LCDOFF 0x01 #define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78 #define HD64461_GPBDR_LED_RED 0x80 #include <asm/hd64461.h> #include <asm/io.h> #define PJDR 0xa4000130 #define PKDR 0xa4000132 #endif /* __ASM_SH_HP6XX_H */ PK �h�Z�� �� � r2d.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_RTS7751R2D_H #define __ASM_SH_RENESAS_RTS7751R2D_H /* * linux/include/asm-sh/renesas_rts7751r2d.h * * Copyright (C) 2000 Atom Create Engineering Co., Ltd. * * Renesas Technology Sales RTS7751R2D support */ /* Board specific addresses. */ #define PA_BCR 0xa4000000 /* FPGA */ #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ #define PA_CFCTL 0xa4000004 /* CF Timing control */ #define PA_CFPOW 0xa4000006 /* CF Power control */ #define PA_DISPCTL 0xa4000008 /* Display Timing control */ #define PA_SDMPOW 0xa400000a /* SD Power control */ #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ #define PA_PCICD 0xa400000e /* PCI Extension detect control */ #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ #define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */ #define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */ #define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ #define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ #define PA_VERREG 0xa4000032 /* FPGA Version Register */ #define PA_INPORT 0xa4000034 /* KEY Input Port control */ #define PA_OUTPORT 0xa4000036 /* LED control */ #define PA_BVERREG 0xa4000038 /* Board Revision Register */ #define PA_AX88796L 0xaa000400 /* AX88796L Area */ #define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ #define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ #define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define R2D_FPGA_IRQ_BASE 100 #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) #define IRQ_TP (R2D_FPGA_IRQ_BASE + 2) #define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3) #define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4) #define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5) #define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6) #define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7) #define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8) #define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9) #define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10) #define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11) #define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12) #define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13) /* arch/sh/boards/renesas/rts7751r2d/irq.c */ void init_rts7751r2d_IRQ(void); int rts7751r2d_irq_demux(int); #endif /* __ASM_SH_RENESAS_RTS7751R2D */ PK �h�Zal3� titan.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ /* * Platform definitions for Titan */ #ifndef _ASM_SH_TITAN_H #define _ASM_SH_TITAN_H #include <linux/sh_intc.h> #define __IO_PREFIX titan #include <asm/io_generic.h> /* IRQ assignments */ #define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */ #define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */ #define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */ #define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */ #define TITAN_IRQ_USB evt2irq(0x360) /* USB */ #endif /* __ASM_SH_TITAN_H */ PK �h�Z��s� sh7785lcr.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_RENESAS_SH7785LCR_H #define __ASM_SH_RENESAS_SH7785LCR_H /* * This board has 2 physical memory maps. * It can be changed with DIP switch(S2-5). * * phys address | S2-5 = OFF | S2-5 = ON * -----------------------------+---------------+--------------- * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB * 0x18000000 - 0x1bffffff(CS6) | reserved | SD * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) * */ #define NOR_FLASH_ADDR 0x00000000 #define NOR_FLASH_SIZE 0x04000000 #define PLD_BASE_ADDR 0x04000000 #define PLD_PCICR (PLD_BASE_ADDR + 0x00) #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02) #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04) #define PLD_POFCR (PLD_BASE_ADDR + 0x06) #define PLD_LEDCR (PLD_BASE_ADDR + 0x08) #define PLD_SWSR (PLD_BASE_ADDR + 0x0a) #define PLD_VERSR (PLD_BASE_ADDR + 0x0c) #define PLD_MMSR (PLD_BASE_ADDR + 0x0e) #define PCA9564_ADDR 0x06000000 /* I2C */ #define PCA9564_SIZE 0x00000100 #define PCA9564_PROTO_32BIT_ADDR 0x14000000 #define SM107_MEM_ADDR 0x10000000 #define SM107_MEM_SIZE 0x00e00000 #define SM107_REG_ADDR 0x13e00000 #define SM107_REG_SIZE 0x00200000 #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) #define R8A66597_ADDR 0x14000000 /* USB */ #define CG200_ADDR 0x18000000 /* SD */ #else #define R8A66597_ADDR 0x08000000 #define CG200_ADDR 0x0c000000 #endif #define R8A66597_SIZE 0x00000100 #define CG200_SIZE 0x00010000 #endif /* __ASM_SH_RENESAS_SH7785LCR_H */ PK �h�Z��� secureedge5410.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 * * include/asm-sh/snapgear.h * * Modified version of io_se.h for the snapgear-specific functions. * * IO functions for a SnapGear */ #ifndef _ASM_SH_IO_SNAPGEAR_H #define _ASM_SH_IO_SNAPGEAR_H #define __IO_PREFIX snapgear #include <asm/io_generic.h> /* * We need to remember what was written to the ioport as some bits * are shared with other functions and you cannot read back what was * written :-| * * Bit Read Write * ----------------------------------------------- * D0 DCD on ttySC1 power * D1 Reset Switch heatbeat * D2 ttySC0 CTS (7100) LAN * D3 - WAN * D4 ttySC0 DCD (7100) CONSOLE * D5 - ONLINE * D6 - VPN * D7 - DTR on ttySC1 * D8 - ttySC0 RTS (7100) * D9 - ttySC0 DTR (7100) * D10 - RTC SCLK * D11 RTC DATA RTC DATA * D12 - RTS RESET */ #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) extern unsigned short secureedge5410_ioport; #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ (secureedge5410_ioport = \ ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) #define SECUREEDGE_READ_IOPORT() \ ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) #endif /* _ASM_SH_IO_SNAPGEAR_H */ PK �h�Z�HK�J J lboxre2.hnu �[��� /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_SH_LBOXRE2_H #define __ASM_SH_LBOXRE2_H /* * Copyright (C) 2007 Nobuhiro Iwamatsu * * NTT COMWARE L-BOX RE2 support */ #include <linux/sh_intc.h> #define IRQ_CF1 evt2irq(0x320) /* CF1 */ #define IRQ_CF0 evt2irq(0x340) /* CF0 */ #define IRQ_INTD evt2irq(0x360) /* INTD */ #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */ #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */ #define IRQ_INTA evt2irq(0x3c0) /* INTA */ void init_lboxre2_IRQ(void); #define __IO_PREFIX lboxre2 #include <asm/io_generic.h> #endif /* __ASM_SH_LBOXRE2_H */ PK �h�ZJ�8�� � shmin.hnu �[��� PK �h�Z|� ̤ � � sh7763rdp.hnu �[��� PK �h�Z� �]� � � romimage.hnu �[��� PK �h�Z�>��� � � microdev.hnu �[��� PK �h�Z�'yn� � � mangle-port.hnu �[��� PK �h�Z�aS� � � sh2007.hnu �[��� PK �h�Z.V� � �' sdk7780.hnu �[��� PK �h�Z�)}' }' z3 highlander.hnu �[��� PK �h�Z:�W�� � 3[ urquell.hnu �[��� PK �h�Ze��b g magicpanelr2.hnu �[��� PK �h�ZL�|�Y Y dn hp6xx.hnu �[��� PK �h�Z�� �� � �s r2d.hnu �[��� PK �h�Zal3� ( titan.hnu �[��� PK �h�Z��s� p� sh7785lcr.hnu �[��� PK �h�Z��� �� secureedge5410.hnu �[��� PK �h�Z�HK�J J � lboxre2.hnu �[��� PK � ��
| ver. 1.4 |
Github
|
.
| PHP 8.2.28 | Generation time: 0.02 |
proxy
|
phpinfo
|
Settings