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usr/src/linux-headers-5.15.0-133/arch/parisc/include/asm/mmu.h 0000644 00000000303 15030301624 0017302 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _PARISC_MMU_H_ #define _PARISC_MMU_H_ /* On parisc, we store the space id here */ typedef unsigned long mm_context_t; #endif /* _PARISC_MMU_H_ */ usr/src/linux-headers-5.15.0-133/arch/openrisc/include/asm/mmu.h 0000644 00000001011 15030347164 0017651 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OpenRISC Linux * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * OpenRISC implementation: * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> * et al. */ #ifndef __ASM_OPENRISC_MMU_H #define __ASM_OPENRISC_MMU_H #ifndef __ASSEMBLY__ typedef unsigned long mm_context_t; #endif #endif usr/src/linux-headers-5.15.0-133/arch/nios2/include/asm/mmu.h 0000644 00000000675 15030347266 0017103 0 ustar 00 /* * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch> * Copyright (C) 2004 Microtronix Datacom Ltd. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef _ASM_NIOS2_MMU_H #define _ASM_NIOS2_MMU_H /* Default "unsigned long" context */ typedef unsigned long mm_context_t; #endif /* _ASM_NIOS2_MMU_H */ usr/src/linux-headers-5.15.0-133/arch/alpha/include/asm/mmu.h 0000644 00000000313 15030401205 0017103 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ALPHA_MMU_H #define __ALPHA_MMU_H /* The alpha MMU context is one "unsigned long" bitmap per CPU */ typedef unsigned long mm_context_t[NR_CPUS]; #endif usr/src/linux-headers-5.15.0-133/arch/um/include/asm/mmu.h 0000644 00000001012 15030475324 0016451 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com) */ #ifndef __ARCH_UM_MMU_H #define __ARCH_UM_MMU_H #include <mm_id.h> #include <asm/mm_context.h> typedef struct mm_context { struct mm_id id; struct uml_arch_mm_context arch; struct page *stub_pages[2]; } mm_context_t; /* Avoid tangled inclusion with asm/ldt.h */ extern long init_new_ldt(struct mm_context *to_mm, struct mm_context *from_mm); extern void free_ldt(struct mm_context *mm); #endif usr/src/linux-headers-5.15.0-133/arch/riscv/include/asm/mmu.h 0000644 00000001142 15030477174 0017167 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2012 Regents of the University of California */ #ifndef _ASM_RISCV_MMU_H #define _ASM_RISCV_MMU_H #ifndef __ASSEMBLY__ typedef struct { #ifndef CONFIG_MMU unsigned long end_brk; #else atomic_long_t id; #endif void *vdso; #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; #endif } mm_context_t; void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot); #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_MMU_H */ usr/src/linux-headers-5.15.0-142/arch/openrisc/include/asm/mmu.h 0000644 00000001011 15030515613 0017645 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OpenRISC Linux * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * OpenRISC implementation: * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> * et al. */ #ifndef __ASM_OPENRISC_MMU_H #define __ASM_OPENRISC_MMU_H #ifndef __ASSEMBLY__ typedef unsigned long mm_context_t; #endif #endif usr/src/linux-headers-5.15.0-141/arch/nios2/include/asm/mmu.h 0000644 00000000675 15030521552 0017072 0 ustar 00 /* * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch> * Copyright (C) 2004 Microtronix Datacom Ltd. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #ifndef _ASM_NIOS2_MMU_H #define _ASM_NIOS2_MMU_H /* Default "unsigned long" context */ typedef unsigned long mm_context_t; #endif /* _ASM_NIOS2_MMU_H */ usr/src/linux-headers-5.15.0-141/arch/parisc/include/asm/mmu.h 0000644 00000000303 15030523453 0017307 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _PARISC_MMU_H_ #define _PARISC_MMU_H_ /* On parisc, we store the space id here */ typedef unsigned long mm_context_t; #endif /* _PARISC_MMU_H_ */ usr/src/linux-headers-5.15.0-133/arch/mips/include/asm/mmu.h 0000644 00000001053 15030523521 0016776 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_MMU_H #define __ASM_MMU_H #include <linux/atomic.h> #include <linux/spinlock.h> #include <linux/wait.h> typedef struct { union { u64 asid[NR_CPUS]; atomic64_t mmid; }; void *vdso; /* lock to be held whilst modifying fp_bd_emupage_allocmap */ spinlock_t bd_emupage_lock; /* bitmap tracking allocation of fp_bd_emupage */ unsigned long *bd_emupage_allocmap; /* wait queue for threads requiring an emuframe */ wait_queue_head_t bd_emupage_queue; } mm_context_t; #endif /* __ASM_MMU_H */ usr/src/linux-headers-5.15.0-142/arch/parisc/include/asm/mmu.h 0000644 00000000303 15030561115 0017305 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _PARISC_MMU_H_ #define _PARISC_MMU_H_ /* On parisc, we store the space id here */ typedef unsigned long mm_context_t; #endif /* _PARISC_MMU_H_ */ usr/src/linux-headers-5.15.0-142/arch/arm64/include/asm/mmu.h 0000644 00000004654 15030567521 0017001 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2012 ARM Ltd. */ #ifndef __ASM_MMU_H #define __ASM_MMU_H #include <asm/cputype.h> #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ #define USER_ASID_BIT 48 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) #define TTBR_ASID_MASK (UL(0xffff) << 48) #ifndef __ASSEMBLY__ #include <linux/refcount.h> typedef struct { atomic64_t id; #ifdef CONFIG_COMPAT void *sigpage; #endif refcount_t pinned; void *vdso; unsigned long flags; } mm_context_t; /* * We use atomic64_read() here because the ASID for an 'mm_struct' can * be reallocated when scheduling one of its threads following a * rollover event (see new_context() and flush_context()). In this case, * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush()) * may use a stale ASID. This is fine in principle as the new ASID is * guaranteed to be clean in the TLB, but the TLBI routines have to take * care to handle the following race: * * CPU 0 CPU 1 CPU 2 * * // ptep_clear_flush(mm) * xchg_relaxed(pte, 0) * DSB ISHST * old = ASID(mm) * | <rollover> * | new = new_context(mm) * \-----------------> atomic_set(mm->context.id, new) * cpu_switch_mm(mm) * // Hardware walk of pte using new ASID * TLBI(old) * * In this scenario, the barrier on CPU 0 and the dependency on CPU 1 * ensure that the page-table walker on CPU 1 *must* see the invalid PTE * written by CPU 0. */ #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) static inline bool arm64_kernel_unmapped_at_el0(void) { return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0); } extern void arm64_memblock_init(void); extern void paging_init(void); extern void bootmem_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, unsigned long virt, phys_addr_t size, pgprot_t prot, bool page_mappings_only); extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot); extern void mark_linear_text_alias_ro(void); extern bool kaslr_requires_kpti(void); #define INIT_MM_CONTEXT(name) \ .pgd = init_pg_dir, #endif /* !__ASSEMBLY__ */ #endif usr/src/linux-headers-5.15.0-141/arch/arc/include/asm/mmu.h 0000644 00000000603 15030567610 0016601 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) */ #ifndef _ASM_ARC_MMU_H #define _ASM_ARC_MMU_H #ifndef __ASSEMBLY__ #include <linux/threads.h> /* NR_CPUS */ typedef struct { unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ } mm_context_t; #endif #include <asm/mmu-arcv2.h> #endif usr/src/linux-headers-5.15.0-133/arch/xtensa/include/asm/mmu.h 0000644 00000000716 15030571034 0017337 0 ustar 00 /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2013 Tensilica Inc. */ #ifndef _XTENSA_MMU_H #define _XTENSA_MMU_H #ifndef CONFIG_MMU #include <asm-generic/mmu.h> #else typedef struct { unsigned long asid[NR_CPUS]; unsigned int cpu; } mm_context_t; #endif /* CONFIG_MMU */ #endif /* _XTENSA_MMU_H */ usr/src/linux-headers-5.15.0-142/arch/riscv/include/asm/mmu.h 0000644 00000001142 15030575301 0017156 0 ustar 00 /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2012 Regents of the University of California */ #ifndef _ASM_RISCV_MMU_H #define _ASM_RISCV_MMU_H #ifndef __ASSEMBLY__ typedef struct { #ifndef CONFIG_MMU unsigned long end_brk; #else atomic_long_t id; #endif void *vdso; #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; #endif } mm_context_t; void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot); #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_MMU_H */
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